1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/clock/stm32mp13-clksrc.h> 9#include <dt-bindings/firewall/stm32mp13-etzpc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 12#include <dt-bindings/reset/stm32mp13-resets.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 compatible = "arm,cortex-a7"; 24 device_type = "cpu"; 25 reg = <0>; 26 clocks = <&rcc CK_MPU>; 27 clock-names = "cpu"; 28 operating-points-v2 = <&cpu0_opp_table>; 29 nvmem-cells = <&part_number_otp>; 30 nvmem-cell-names = "part_number"; 31 }; 32 }; 33 34 cpu0_opp_table: cpu0-opp-table { 35 compatible = "operating-points-v2"; 36 37 /* Non‑overdrive OPP mission profile */ 38 opp-650000000 { 39 opp-hz = /bits/ 64 <650000000>; 40 opp-microvolt = <1250000>; 41 opp-supported-hw = <0x3>; 42 st,opp-default; 43 }; 44 45 /* Overdrive OPP: 10‑year life activity @100% activity rate */ 46 opp-900000000 { 47 opp-hz = /bits/ 64 <900000000>; 48 opp-microvolt = <1350000>; 49 opp-supported-hw = <0x2>; 50 st,opp-default; 51 }; 52 53 /* Overdrive OPP: 10‑year life activity @25% activity rate */ 54 opp-1000000000 { 55 opp-hz = /bits/ 64 <1000000000>; 56 opp-microvolt = <1350000>; 57 opp-supported-hw = <0x2>; 58 }; 59 }; 60 61 hse_monitor: hse-monitor { 62 compatible = "st,freq-monitor"; 63 counter = <&lptimer3 1 1 0 0>; 64 status = "disabled"; 65 }; 66 67 intc: interrupt-controller@a0021000 { 68 compatible = "arm,cortex-a7-gic"; 69 #interrupt-cells = <3>; 70 interrupt-controller; 71 reg = <0xa0021000 0x1000>, 72 <0xa0022000 0x2000>; 73 }; 74 75 psci { 76 compatible = "arm,psci-1.0"; 77 method = "smc"; 78 }; 79 80 clocks { 81 clk_hse: clk-hse { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <24000000>; 85 }; 86 87 clk_hsi: clk-hsi { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <64000000>; 91 }; 92 93 clk_lse: clk-lse { 94 #clock-cells = <0>; 95 compatible = "fixed-clock"; 96 clock-frequency = <32768>; 97 }; 98 99 clk_lsi: clk-lsi { 100 #clock-cells = <0>; 101 compatible = "fixed-clock"; 102 clock-frequency = <32000>; 103 }; 104 105 clk_csi: clk-csi { 106 #clock-cells = <0>; 107 compatible = "fixed-clock"; 108 clock-frequency = <4000000>; 109 }; 110 111 clk_i2sin: clk-i2sin { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 clock-frequency = <19000000>; 115 }; 116 117 }; 118 119 sdmmc1_io: sdmmc1_io { 120 compatible = "st,stm32mp13-iod"; 121 regulator-name = "sdmmc1_io"; 122 regulator-always-on; 123 }; 124 125 sdmmc2_io: sdmmc2_io { 126 compatible = "st,stm32mp13-iod"; 127 regulator-name = "sdmmc2_io"; 128 regulator-always-on; 129 }; 130 131 soc { 132 compatible = "simple-bus"; 133 #address-cells = <1>; 134 #size-cells = <1>; 135 interrupt-parent = <&intc>; 136 ranges; 137 138 usart3: serial@4000f000 { 139 compatible = "st,stm32h7-uart"; 140 reg = <0x4000f000 0x400>; 141 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&rcc USART3_K>; 143 resets = <&rcc USART3_R>; 144 status = "disabled"; 145 }; 146 147 uart4: serial@40010000 { 148 compatible = "st,stm32h7-uart"; 149 reg = <0x40010000 0x400>; 150 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 151 clocks = <&rcc UART4_K>; 152 resets = <&rcc UART4_R>; 153 status = "disabled"; 154 }; 155 156 uart5: serial@40011000 { 157 compatible = "st,stm32h7-uart"; 158 reg = <0x40011000 0x400>; 159 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&rcc UART5_K>; 161 resets = <&rcc UART5_R>; 162 status = "disabled"; 163 }; 164 165 uart7: serial@40018000 { 166 compatible = "st,stm32h7-uart"; 167 reg = <0x40018000 0x400>; 168 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&rcc UART7_K>; 170 resets = <&rcc UART7_R>; 171 status = "disabled"; 172 }; 173 174 uart8: serial@40019000 { 175 compatible = "st,stm32h7-uart"; 176 reg = <0x40019000 0x400>; 177 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&rcc UART8_K>; 179 resets = <&rcc UART8_R>; 180 status = "disabled"; 181 }; 182 183 usart6: serial@44003000 { 184 compatible = "st,stm32h7-uart"; 185 reg = <0x44003000 0x400>; 186 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&rcc USART6_K>; 188 resets = <&rcc USART6_R>; 189 status = "disabled"; 190 }; 191 192 rcc: rcc@50000000 { 193 compatible = "st,stm32mp13-rcc", "syscon"; 194 reg = <0x50000000 0x1000>; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 #clock-cells = <1>; 198 #reset-cells = <1>; 199 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, <&clk_lsi>, <&clk_csi>, <&clk_i2sin>; 200 clock-names = "clk-hse", "clk-hsi", "clk-lse", "clk-lsi", "clk-csi", "clk-i2sin"; 201 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 202 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 203 secure-interrupt-names = "wakeup"; 204 }; 205 206 pwr_regulators: pwr@50001000 { 207 compatible = "st,stm32mp1,pwr-reg"; 208 reg = <0x50001000 0x10>; 209 210 reg11: reg11 { 211 regulator-name = "reg11"; 212 regulator-min-microvolt = <1100000>; 213 regulator-max-microvolt = <1100000>; 214 }; 215 216 reg18: reg18 { 217 regulator-name = "reg18"; 218 regulator-min-microvolt = <1800000>; 219 regulator-max-microvolt = <1800000>; 220 }; 221 222 usb33: usb33 { 223 regulator-name = "usb33"; 224 regulator-min-microvolt = <3300000>; 225 regulator-max-microvolt = <3300000>; 226 }; 227 }; 228 229 pwr_irq: pwr@50001010 { 230 compatible = "st,stm32mp1,pwr-irq"; 231 status = "disabled"; 232 }; 233 234 syscfg: syscon@50020000 { 235 compatible = "st,stm32mp157-syscfg", "syscon"; 236 reg = <0x50020000 0x400>; 237 }; 238 239 iwdg2: watchdog@5a002000 { 240 compatible = "st,stm32mp1-iwdg"; 241 reg = <0x5a002000 0x400>; 242 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 244 clock-names = "pclk", "lsi"; 245 status = "disabled"; 246 }; 247 248 rtc: rtc@5c004000 { 249 compatible = "st,stm32mp13-rtc"; 250 reg = <0x5c004000 0x400>; 251 clocks = <&rcc RTCAPB>, <&rcc RTC>; 252 clock-names = "pclk", "rtc_ck"; 253 status = "disabled"; 254 }; 255 256 bsec: efuse@5c005000 { 257 compatible = "st,stm32mp13-bsec"; 258 reg = <0x5c005000 0x400>; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 262 cfg0_otp: cfg0_otp@0 { 263 reg = <0x0 0x2>; 264 }; 265 part_number_otp: part_number_otp@4 { 266 reg = <0x4 0x2>; 267 bits = <0 12>; 268 }; 269 monotonic_otp: monotonic_otp@10 { 270 reg = <0x10 0x4>; 271 }; 272 nand_otp: cfg9_otp@24 { 273 reg = <0x24 0x4>; 274 }; 275 uid_otp: uid_otp@34 { 276 reg = <0x34 0xc>; 277 }; 278 hw2_otp: hw2_otp@48 { 279 reg = <0x48 0x4>; 280 }; 281 ts_cal1: calib@5c { 282 reg = <0x5c 0x2>; 283 }; 284 ts_cal2: calib@5e { 285 reg = <0x5e 0x2>; 286 }; 287 pkh_otp: pkh_otp@60 { 288 reg = <0x60 0x20>; 289 }; 290 ethernet_mac1_address: mac1@e4 { 291 reg = <0xe4 0xc>; 292 st,non-secure-otp; 293 }; 294 oem_enc_key: oem_enc_key@170 { 295 reg = <0x170 0x10>; 296 }; 297 }; 298 299 tzc400: tzc@5c006000 { 300 compatible = "st,stm32mp1-tzc"; 301 reg = <0x5c006000 0x1000>; 302 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 303 st,mem-map = <0xc0000000 0x40000000>; 304 clocks = <&rcc TZC>; 305 }; 306 307 tamp: tamp@5c00a000 { 308 compatible = "st,stm32mp13-tamp"; 309 reg = <0x5c00a000 0x400>; 310 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&rcc RTCAPB>; 312 st,backup-zones = <10 5 17>; 313 }; 314 315 pinctrl: pin-controller@50002000 { 316 #address-cells = <1>; 317 #size-cells = <1>; 318 compatible = "st,stm32mp135-pinctrl"; 319 ranges = <0 0x50002000 0x8400>; 320 pins-are-numbered; 321 322 gpioa: gpio@50002000 { 323 gpio-controller; 324 #gpio-cells = <2>; 325 interrupt-controller; 326 #interrupt-cells = <2>; 327 #access-controller-cells = <1>; 328 clocks = <&rcc GPIOA>; 329 reg = <0x0 0x400>; 330 st,bank-name = "GPIOA"; 331 ngpios = <16>; 332 gpio-ranges = <&pinctrl 0 0 16>; 333 }; 334 335 gpiob: gpio@50003000 { 336 gpio-controller; 337 #gpio-cells = <2>; 338 interrupt-controller; 339 #interrupt-cells = <2>; 340 #access-controller-cells = <1>; 341 clocks = <&rcc GPIOB>; 342 reg = <0x1000 0x400>; 343 st,bank-name = "GPIOB"; 344 ngpios = <16>; 345 gpio-ranges = <&pinctrl 0 16 16>; 346 }; 347 348 gpioc: gpio@50004000 { 349 gpio-controller; 350 #gpio-cells = <2>; 351 interrupt-controller; 352 #interrupt-cells = <2>; 353 #access-controller-cells = <1>; 354 clocks = <&rcc GPIOC>; 355 reg = <0x2000 0x400>; 356 st,bank-name = "GPIOC"; 357 ngpios = <16>; 358 gpio-ranges = <&pinctrl 0 32 16>; 359 }; 360 361 gpiod: gpio@50005000 { 362 gpio-controller; 363 #gpio-cells = <2>; 364 interrupt-controller; 365 #interrupt-cells = <2>; 366 #access-controller-cells = <1>; 367 clocks = <&rcc GPIOD>; 368 reg = <0x3000 0x400>; 369 st,bank-name = "GPIOD"; 370 ngpios = <16>; 371 gpio-ranges = <&pinctrl 0 48 16>; 372 }; 373 374 gpioe: gpio@50006000 { 375 gpio-controller; 376 #gpio-cells = <2>; 377 interrupt-controller; 378 #interrupt-cells = <2>; 379 #access-controller-cells = <1>; 380 clocks = <&rcc GPIOE>; 381 reg = <0x4000 0x400>; 382 st,bank-name = "GPIOE"; 383 ngpios = <16>; 384 gpio-ranges = <&pinctrl 0 64 16>; 385 }; 386 387 gpiof: gpio@50007000 { 388 gpio-controller; 389 #gpio-cells = <2>; 390 interrupt-controller; 391 #interrupt-cells = <2>; 392 #access-controller-cells = <1>; 393 clocks = <&rcc GPIOF>; 394 reg = <0x5000 0x400>; 395 st,bank-name = "GPIOF"; 396 ngpios = <16>; 397 gpio-ranges = <&pinctrl 0 80 16>; 398 }; 399 400 gpiog: gpio@50008000 { 401 gpio-controller; 402 #gpio-cells = <2>; 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 #access-controller-cells = <1>; 406 clocks = <&rcc GPIOG>; 407 reg = <0x6000 0x400>; 408 st,bank-name = "GPIOG"; 409 ngpios = <16>; 410 gpio-ranges = <&pinctrl 0 96 16>; 411 }; 412 413 gpioh: gpio@50009000 { 414 gpio-controller; 415 #gpio-cells = <2>; 416 interrupt-controller; 417 #interrupt-cells = <2>; 418 #access-controller-cells = <1>; 419 clocks = <&rcc GPIOH>; 420 reg = <0x7000 0x400>; 421 st,bank-name = "GPIOH"; 422 ngpios = <15>; 423 gpio-ranges = <&pinctrl 0 112 15>; 424 }; 425 426 gpioi: gpio@5000a000 { 427 gpio-controller; 428 #gpio-cells = <2>; 429 interrupt-controller; 430 #interrupt-cells = <2>; 431 #access-controller-cells = <1>; 432 clocks = <&rcc GPIOI>; 433 reg = <0x8000 0x400>; 434 st,bank-name = "GPIOI"; 435 ngpios = <8>; 436 gpio-ranges = <&pinctrl 0 128 8>; 437 }; 438 }; 439 440 etzpc: etzpc@5c007000 { 441 compatible = "st,stm32-etzpc", "simple-bus"; 442 reg = <0x5C007000 0x400>; 443 clocks = <&rcc TZPC>; 444 #address-cells = <1>; 445 #size-cells = <1>; 446 #access-controller-cells = <1>; 447 448 adc_2: adc@48004000 { 449 reg = <0x48004000 0x400>; 450 compatible = "st,stm32mp13-adc-core"; 451 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 453 clock-names = "bus", "adc"; 454 interrupt-controller; 455 #interrupt-cells = <1>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 access-controllers = <&etzpc STM32MP1_ETZPC_ADC2_ID>; 459 status = "disabled"; 460 461 adc2: adc@0 { 462 compatible = "st,stm32mp13-adc"; 463 reg = <0x0>; 464 #io-channel-cells = <1>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 interrupt-parent = <&adc_2>; 468 interrupts = <0>; 469 status = "disabled"; 470 471 channel@13 { 472 reg = <13>; 473 label = "vrefint"; 474 }; 475 476 channel@14 { 477 reg = <14>; 478 label = "vddcore"; 479 }; 480 481 channel@16 { 482 reg = <16>; 483 label = "vddcpu"; 484 }; 485 486 channel@17 { 487 reg = <17>; 488 label = "vddq_ddr"; 489 }; 490 }; 491 }; 492 493 usart1: serial@4c000000 { 494 compatible = "st,stm32h7-uart"; 495 reg = <0x4c000000 0x400>; 496 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&rcc USART1_K>; 498 resets = <&rcc USART1_R>; 499 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 500 status = "disabled"; 501 }; 502 503 usart2: serial@4c001000 { 504 compatible = "st,stm32h7-uart"; 505 reg = <0x4c001000 0x400>; 506 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&rcc USART2_K>; 508 resets = <&rcc USART2_R>; 509 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 510 status = "disabled"; 511 }; 512 513 i2c3: i2c@4c004000 { 514 compatible = "st,stm32mp13-i2c"; 515 reg = <0x4c004000 0x400>; 516 clocks = <&rcc I2C3_K>; 517 resets = <&rcc I2C3_R>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 st,syscfg-fmp = <&syscfg 0x4 0x4>; 521 i2c-analog-filter; 522 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 523 status = "disabled"; 524 }; 525 526 i2c4: i2c@4c005000 { 527 compatible = "st,stm32mp13-i2c"; 528 reg = <0x4c005000 0x400>; 529 clocks = <&rcc I2C4_K>; 530 resets = <&rcc I2C4_R>; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 st,syscfg-fmp = <&syscfg 0x4 0x8>; 534 i2c-analog-filter; 535 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 536 status = "disabled"; 537 }; 538 539 i2c5: i2c@4c006000 { 540 compatible = "st,stm32mp13-i2c"; 541 reg = <0x4c006000 0x400>; 542 clocks = <&rcc I2C5_K>; 543 resets = <&rcc I2C5_R>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 st,syscfg-fmp = <&syscfg 0x4 0x10>; 547 i2c-analog-filter; 548 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 549 status = "disabled"; 550 }; 551 552 timers12: timer@4c007000 { 553 #address-cells = <1>; 554 #size-cells = <0>; 555 compatible = "st,stm32-timers"; 556 reg = <0x4c007000 0x400>; 557 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&rcc TIM12_K>; 559 clock-names = "int"; 560 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 561 status = "disabled"; 562 563 counter { 564 compatible = "st,stm32-timer-counter"; 565 status = "disabled"; 566 }; 567 }; 568 569 timers13: timer@4c008000 { 570 #address-cells = <1>; 571 #size-cells = <0>; 572 compatible = "st,stm32-timers"; 573 reg = <0x4c008000 0x400>; 574 clocks = <&rcc TIM13_K>; 575 clock-names = "int"; 576 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 577 status = "disabled"; 578 }; 579 580 timers14: timer@4c009000 { 581 #address-cells = <1>; 582 #size-cells = <0>; 583 compatible = "st,stm32-timers"; 584 reg = <0x4c009000 0x400>; 585 clocks = <&rcc TIM14_K>; 586 clock-names = "int"; 587 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 588 status = "disabled"; 589 }; 590 591 timers15: timer@4c00a000 { 592 #address-cells = <1>; 593 #size-cells = <0>; 594 compatible = "st,stm32-timers"; 595 reg = <0x4c00a000 0x400>; 596 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&rcc TIM15_K>; 598 clock-names = "int"; 599 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 600 status = "disabled"; 601 602 counter { 603 compatible = "st,stm32-timer-counter"; 604 status = "disabled"; 605 }; 606 }; 607 608 timers16: timer@4c00b000 { 609 #address-cells = <1>; 610 #size-cells = <0>; 611 compatible = "st,stm32-timers"; 612 reg = <0x4c00b000 0x400>; 613 clocks = <&rcc TIM16_K>; 614 clock-names = "int"; 615 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 616 status = "disabled"; 617 }; 618 619 timers17: timer@4c00c000 { 620 #address-cells = <1>; 621 #size-cells = <0>; 622 compatible = "st,stm32-timers"; 623 reg = <0x4c00c000 0x400>; 624 clocks = <&rcc TIM17_K>; 625 clock-names = "int"; 626 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 627 status = "disabled"; 628 }; 629 630 lptimer2: timer@50021000 { 631 #address-cells = <1>; 632 #size-cells = <0>; 633 compatible = "st,stm32-lptimer"; 634 reg = <0x50021000 0x400>; 635 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&rcc LPTIM2_K>; 637 clock-names = "mux"; 638 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 639 status = "disabled"; 640 }; 641 642 lptimer3: timer@50022000 { 643 #address-cells = <1>; 644 #size-cells = <0>; 645 compatible = "st,stm32-lptimer"; 646 reg = <0x50022000 0x400>; 647 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&rcc LPTIM3_K>; 649 clock-names = "mux"; 650 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 651 status = "disabled"; 652 653 counter { 654 compatible = "st,stm32-lptimer-counter"; 655 status = "disabled"; 656 }; 657 }; 658 659 vrefbuf: vrefbuf@50025000 { 660 compatible = "st,stm32mp13-vrefbuf"; 661 reg = <0x50025000 0x8>; 662 regulator-name = "vrefbuf"; 663 regulator-min-microvolt = <1650000>; 664 regulator-max-microvolt = <2500000>; 665 clocks = <&rcc VREF>; 666 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 667 status = "disabled"; 668 }; 669 670 hash: hash@54003000 { 671 compatible = "st,stm32mp13-hash"; 672 reg = <0x54003000 0x400>; 673 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&rcc HASH1>; 675 resets = <&rcc HASH1_R>; 676 access-controllers = <&etzpc STM32MP1_ETZPC_HASH_ID>; 677 status = "disabled"; 678 }; 679 680 rng: rng@54004000 { 681 compatible = "st,stm32mp13-rng"; 682 reg = <0x54004000 0x400>; 683 clocks = <&rcc RNG1_K>; 684 resets = <&rcc RNG1_R>; 685 access-controllers = <&etzpc STM32MP1_ETZPC_RNG_ID>; 686 status = "disabled"; 687 }; 688 689 iwdg1: watchdog@5c003000 { 690 compatible = "st,stm32mp1-iwdg"; 691 reg = <0x5C003000 0x400>; 692 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 694 clock-names = "pclk", "lsi"; 695 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 696 status = "disabled"; 697 }; 698 699 stgen: stgen@5c008000 { 700 compatible = "st,stm32-stgen"; 701 reg = <0x5C008000 0x1000>; 702 access-controllers = <&etzpc STM32MP1_ETZPC_STGENC_ID>; 703 }; 704 }; 705 }; 706}; 707