1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/clock/stm32mp13-clksrc.h> 9#include <dt-bindings/firewall/stm32mp13-etzpc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 12#include <dt-bindings/reset/stm32mp13-resets.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 compatible = "arm,cortex-a7"; 24 device_type = "cpu"; 25 reg = <0>; 26 }; 27 }; 28 29 hse_monitor: hse-monitor { 30 compatible = "st,freq-monitor"; 31 counter = <&lptimer3 1 1 0 0>; 32 status = "disabled"; 33 }; 34 35 intc: interrupt-controller@a0021000 { 36 compatible = "arm,cortex-a7-gic"; 37 #interrupt-cells = <3>; 38 interrupt-controller; 39 reg = <0xa0021000 0x1000>, 40 <0xa0022000 0x2000>; 41 }; 42 43 psci { 44 compatible = "arm,psci-1.0"; 45 method = "smc"; 46 }; 47 48 clocks { 49 clk_hse: clk-hse { 50 #clock-cells = <0>; 51 compatible = "fixed-clock"; 52 clock-frequency = <24000000>; 53 }; 54 55 clk_hsi: clk-hsi { 56 #clock-cells = <0>; 57 compatible = "fixed-clock"; 58 clock-frequency = <64000000>; 59 }; 60 61 clk_lse: clk-lse { 62 #clock-cells = <0>; 63 compatible = "fixed-clock"; 64 clock-frequency = <32768>; 65 }; 66 67 clk_lsi: clk-lsi { 68 #clock-cells = <0>; 69 compatible = "fixed-clock"; 70 clock-frequency = <32000>; 71 }; 72 73 clk_csi: clk-csi { 74 #clock-cells = <0>; 75 compatible = "fixed-clock"; 76 clock-frequency = <4000000>; 77 }; 78 79 clk_i2sin: clk-i2sin { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <19000000>; 83 }; 84 85 }; 86 87 sdmmc1_io: sdmmc1_io { 88 compatible = "st,stm32mp13-iod"; 89 regulator-name = "sdmmc1_io"; 90 regulator-always-on; 91 }; 92 93 sdmmc2_io: sdmmc2_io { 94 compatible = "st,stm32mp13-iod"; 95 regulator-name = "sdmmc2_io"; 96 regulator-always-on; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 interrupt-parent = <&intc>; 104 ranges; 105 106 usart3: serial@4000f000 { 107 compatible = "st,stm32h7-uart"; 108 reg = <0x4000f000 0x400>; 109 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&rcc USART3_K>; 111 resets = <&rcc USART3_R>; 112 status = "disabled"; 113 }; 114 115 uart4: serial@40010000 { 116 compatible = "st,stm32h7-uart"; 117 reg = <0x40010000 0x400>; 118 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&rcc UART4_K>; 120 resets = <&rcc UART4_R>; 121 status = "disabled"; 122 }; 123 124 uart5: serial@40011000 { 125 compatible = "st,stm32h7-uart"; 126 reg = <0x40011000 0x400>; 127 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 128 clocks = <&rcc UART5_K>; 129 resets = <&rcc UART5_R>; 130 status = "disabled"; 131 }; 132 133 uart7: serial@40018000 { 134 compatible = "st,stm32h7-uart"; 135 reg = <0x40018000 0x400>; 136 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&rcc UART7_K>; 138 resets = <&rcc UART7_R>; 139 status = "disabled"; 140 }; 141 142 uart8: serial@40019000 { 143 compatible = "st,stm32h7-uart"; 144 reg = <0x40019000 0x400>; 145 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&rcc UART8_K>; 147 resets = <&rcc UART8_R>; 148 status = "disabled"; 149 }; 150 151 usart6: serial@44003000 { 152 compatible = "st,stm32h7-uart"; 153 reg = <0x44003000 0x400>; 154 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&rcc USART6_K>; 156 resets = <&rcc USART6_R>; 157 status = "disabled"; 158 }; 159 160 rcc: rcc@50000000 { 161 compatible = "st,stm32mp13-rcc", "syscon"; 162 reg = <0x50000000 0x1000>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 #clock-cells = <1>; 166 #reset-cells = <1>; 167 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, <&clk_lsi>, <&clk_csi>, <&clk_i2sin>; 168 clock-names = "clk-hse", "clk-hsi", "clk-lse", "clk-lsi", "clk-csi", "clk-i2sin"; 169 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 170 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 171 secure-interrupt-names = "wakeup"; 172 }; 173 174 pwr_regulators: pwr@50001000 { 175 compatible = "st,stm32mp1,pwr-reg"; 176 reg = <0x50001000 0x10>; 177 178 reg11: reg11 { 179 regulator-name = "reg11"; 180 regulator-min-microvolt = <1100000>; 181 regulator-max-microvolt = <1100000>; 182 }; 183 184 reg18: reg18 { 185 regulator-name = "reg18"; 186 regulator-min-microvolt = <1800000>; 187 regulator-max-microvolt = <1800000>; 188 }; 189 190 usb33: usb33 { 191 regulator-name = "usb33"; 192 regulator-min-microvolt = <3300000>; 193 regulator-max-microvolt = <3300000>; 194 }; 195 }; 196 197 pwr_irq: pwr@50001010 { 198 compatible = "st,stm32mp1,pwr-irq"; 199 status = "disabled"; 200 }; 201 202 syscfg: syscon@50020000 { 203 compatible = "st,stm32mp157-syscfg", "syscon"; 204 reg = <0x50020000 0x400>; 205 }; 206 207 iwdg2: watchdog@5a002000 { 208 compatible = "st,stm32mp1-iwdg"; 209 reg = <0x5a002000 0x400>; 210 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 212 clock-names = "pclk", "lsi"; 213 status = "disabled"; 214 }; 215 216 rtc: rtc@5c004000 { 217 compatible = "st,stm32mp13-rtc"; 218 reg = <0x5c004000 0x400>; 219 clocks = <&rcc RTCAPB>, <&rcc RTC>; 220 clock-names = "pclk", "rtc_ck"; 221 status = "disabled"; 222 }; 223 224 bsec: efuse@5c005000 { 225 compatible = "st,stm32mp13-bsec"; 226 reg = <0x5c005000 0x400>; 227 #address-cells = <1>; 228 #size-cells = <1>; 229 230 cfg0_otp: cfg0_otp@0 { 231 reg = <0x0 0x2>; 232 }; 233 part_number_otp: part_number_otp@4 { 234 reg = <0x4 0x2>; 235 bits = <0 12>; 236 }; 237 monotonic_otp: monotonic_otp@10 { 238 reg = <0x10 0x4>; 239 }; 240 nand_otp: cfg9_otp@24 { 241 reg = <0x24 0x4>; 242 }; 243 uid_otp: uid_otp@34 { 244 reg = <0x34 0xc>; 245 }; 246 hw2_otp: hw2_otp@48 { 247 reg = <0x48 0x4>; 248 }; 249 ts_cal1: calib@5c { 250 reg = <0x5c 0x2>; 251 }; 252 ts_cal2: calib@5e { 253 reg = <0x5e 0x2>; 254 }; 255 pkh_otp: pkh_otp@60 { 256 reg = <0x60 0x20>; 257 }; 258 ethernet_mac1_address: mac1@e4 { 259 reg = <0xe4 0xc>; 260 st,non-secure-otp; 261 }; 262 oem_enc_key: oem_enc_key@170 { 263 reg = <0x170 0x10>; 264 }; 265 }; 266 267 tzc400: tzc@5c006000 { 268 compatible = "st,stm32mp1-tzc"; 269 reg = <0x5c006000 0x1000>; 270 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 271 st,mem-map = <0xc0000000 0x40000000>; 272 clocks = <&rcc TZC>; 273 }; 274 275 tamp: tamp@5c00a000 { 276 compatible = "st,stm32mp13-tamp"; 277 reg = <0x5c00a000 0x400>; 278 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&rcc RTCAPB>; 280 st,backup-zones = <10 5 17>; 281 }; 282 283 pinctrl: pin-controller@50002000 { 284 #address-cells = <1>; 285 #size-cells = <1>; 286 compatible = "st,stm32mp135-pinctrl"; 287 ranges = <0 0x50002000 0x8400>; 288 pins-are-numbered; 289 290 gpioa: gpio@50002000 { 291 gpio-controller; 292 #gpio-cells = <2>; 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 #access-controller-cells = <1>; 296 clocks = <&rcc GPIOA>; 297 reg = <0x0 0x400>; 298 st,bank-name = "GPIOA"; 299 ngpios = <16>; 300 gpio-ranges = <&pinctrl 0 0 16>; 301 }; 302 303 gpiob: gpio@50003000 { 304 gpio-controller; 305 #gpio-cells = <2>; 306 interrupt-controller; 307 #interrupt-cells = <2>; 308 #access-controller-cells = <1>; 309 clocks = <&rcc GPIOB>; 310 reg = <0x1000 0x400>; 311 st,bank-name = "GPIOB"; 312 ngpios = <16>; 313 gpio-ranges = <&pinctrl 0 16 16>; 314 }; 315 316 gpioc: gpio@50004000 { 317 gpio-controller; 318 #gpio-cells = <2>; 319 interrupt-controller; 320 #interrupt-cells = <2>; 321 #access-controller-cells = <1>; 322 clocks = <&rcc GPIOC>; 323 reg = <0x2000 0x400>; 324 st,bank-name = "GPIOC"; 325 ngpios = <16>; 326 gpio-ranges = <&pinctrl 0 32 16>; 327 }; 328 329 gpiod: gpio@50005000 { 330 gpio-controller; 331 #gpio-cells = <2>; 332 interrupt-controller; 333 #interrupt-cells = <2>; 334 #access-controller-cells = <1>; 335 clocks = <&rcc GPIOD>; 336 reg = <0x3000 0x400>; 337 st,bank-name = "GPIOD"; 338 ngpios = <16>; 339 gpio-ranges = <&pinctrl 0 48 16>; 340 }; 341 342 gpioe: gpio@50006000 { 343 gpio-controller; 344 #gpio-cells = <2>; 345 interrupt-controller; 346 #interrupt-cells = <2>; 347 #access-controller-cells = <1>; 348 clocks = <&rcc GPIOE>; 349 reg = <0x4000 0x400>; 350 st,bank-name = "GPIOE"; 351 ngpios = <16>; 352 gpio-ranges = <&pinctrl 0 64 16>; 353 }; 354 355 gpiof: gpio@50007000 { 356 gpio-controller; 357 #gpio-cells = <2>; 358 interrupt-controller; 359 #interrupt-cells = <2>; 360 #access-controller-cells = <1>; 361 clocks = <&rcc GPIOF>; 362 reg = <0x5000 0x400>; 363 st,bank-name = "GPIOF"; 364 ngpios = <16>; 365 gpio-ranges = <&pinctrl 0 80 16>; 366 }; 367 368 gpiog: gpio@50008000 { 369 gpio-controller; 370 #gpio-cells = <2>; 371 interrupt-controller; 372 #interrupt-cells = <2>; 373 #access-controller-cells = <1>; 374 clocks = <&rcc GPIOG>; 375 reg = <0x6000 0x400>; 376 st,bank-name = "GPIOG"; 377 ngpios = <16>; 378 gpio-ranges = <&pinctrl 0 96 16>; 379 }; 380 381 gpioh: gpio@50009000 { 382 gpio-controller; 383 #gpio-cells = <2>; 384 interrupt-controller; 385 #interrupt-cells = <2>; 386 #access-controller-cells = <1>; 387 clocks = <&rcc GPIOH>; 388 reg = <0x7000 0x400>; 389 st,bank-name = "GPIOH"; 390 ngpios = <15>; 391 gpio-ranges = <&pinctrl 0 112 15>; 392 }; 393 394 gpioi: gpio@5000a000 { 395 gpio-controller; 396 #gpio-cells = <2>; 397 interrupt-controller; 398 #interrupt-cells = <2>; 399 #access-controller-cells = <1>; 400 clocks = <&rcc GPIOI>; 401 reg = <0x8000 0x400>; 402 st,bank-name = "GPIOI"; 403 ngpios = <8>; 404 gpio-ranges = <&pinctrl 0 128 8>; 405 }; 406 }; 407 408 etzpc: etzpc@5c007000 { 409 compatible = "st,stm32-etzpc", "simple-bus"; 410 reg = <0x5C007000 0x400>; 411 clocks = <&rcc TZPC>; 412 #address-cells = <1>; 413 #size-cells = <1>; 414 #access-controller-cells = <1>; 415 416 adc_2: adc@48004000 { 417 reg = <0x48004000 0x400>; 418 compatible = "st,stm32mp13-adc-core"; 419 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 421 clock-names = "bus", "adc"; 422 interrupt-controller; 423 #interrupt-cells = <1>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 access-controllers = <&etzpc STM32MP1_ETZPC_ADC2_ID>; 427 status = "disabled"; 428 429 adc2: adc@0 { 430 compatible = "st,stm32mp13-adc"; 431 reg = <0x0>; 432 #io-channel-cells = <1>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 interrupt-parent = <&adc_2>; 436 interrupts = <0>; 437 status = "disabled"; 438 439 channel@13 { 440 reg = <13>; 441 label = "vrefint"; 442 }; 443 444 channel@14 { 445 reg = <14>; 446 label = "vddcore"; 447 }; 448 449 channel@16 { 450 reg = <16>; 451 label = "vddcpu"; 452 }; 453 454 channel@17 { 455 reg = <17>; 456 label = "vddq_ddr"; 457 }; 458 }; 459 }; 460 461 usart1: serial@4c000000 { 462 compatible = "st,stm32h7-uart"; 463 reg = <0x4c000000 0x400>; 464 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&rcc USART1_K>; 466 resets = <&rcc USART1_R>; 467 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 468 status = "disabled"; 469 }; 470 471 usart2: serial@4c001000 { 472 compatible = "st,stm32h7-uart"; 473 reg = <0x4c001000 0x400>; 474 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&rcc USART2_K>; 476 resets = <&rcc USART2_R>; 477 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 478 status = "disabled"; 479 }; 480 481 i2c3: i2c@4c004000 { 482 compatible = "st,stm32mp13-i2c"; 483 reg = <0x4c004000 0x400>; 484 clocks = <&rcc I2C3_K>; 485 resets = <&rcc I2C3_R>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 st,syscfg-fmp = <&syscfg 0x4 0x4>; 489 i2c-analog-filter; 490 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 491 status = "disabled"; 492 }; 493 494 i2c4: i2c@4c005000 { 495 compatible = "st,stm32mp13-i2c"; 496 reg = <0x4c005000 0x400>; 497 clocks = <&rcc I2C4_K>; 498 resets = <&rcc I2C4_R>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 st,syscfg-fmp = <&syscfg 0x4 0x8>; 502 i2c-analog-filter; 503 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 504 status = "disabled"; 505 }; 506 507 i2c5: i2c@4c006000 { 508 compatible = "st,stm32mp13-i2c"; 509 reg = <0x4c006000 0x400>; 510 clocks = <&rcc I2C5_K>; 511 resets = <&rcc I2C5_R>; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 st,syscfg-fmp = <&syscfg 0x4 0x10>; 515 i2c-analog-filter; 516 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 517 status = "disabled"; 518 }; 519 520 timers12: timer@4c007000 { 521 #address-cells = <1>; 522 #size-cells = <0>; 523 compatible = "st,stm32-timers"; 524 reg = <0x4c007000 0x400>; 525 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&rcc TIM12_K>; 527 clock-names = "int"; 528 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 529 status = "disabled"; 530 531 counter { 532 compatible = "st,stm32-timer-counter"; 533 status = "disabled"; 534 }; 535 }; 536 537 timers13: timer@4c008000 { 538 #address-cells = <1>; 539 #size-cells = <0>; 540 compatible = "st,stm32-timers"; 541 reg = <0x4c008000 0x400>; 542 clocks = <&rcc TIM13_K>; 543 clock-names = "int"; 544 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 545 status = "disabled"; 546 }; 547 548 timers14: timer@4c009000 { 549 #address-cells = <1>; 550 #size-cells = <0>; 551 compatible = "st,stm32-timers"; 552 reg = <0x4c009000 0x400>; 553 clocks = <&rcc TIM14_K>; 554 clock-names = "int"; 555 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 556 status = "disabled"; 557 }; 558 559 timers15: timer@4c00a000 { 560 #address-cells = <1>; 561 #size-cells = <0>; 562 compatible = "st,stm32-timers"; 563 reg = <0x4c00a000 0x400>; 564 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&rcc TIM15_K>; 566 clock-names = "int"; 567 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 568 status = "disabled"; 569 570 counter { 571 compatible = "st,stm32-timer-counter"; 572 status = "disabled"; 573 }; 574 }; 575 576 timers16: timer@4c00b000 { 577 #address-cells = <1>; 578 #size-cells = <0>; 579 compatible = "st,stm32-timers"; 580 reg = <0x4c00b000 0x400>; 581 clocks = <&rcc TIM16_K>; 582 clock-names = "int"; 583 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 584 status = "disabled"; 585 }; 586 587 timers17: timer@4c00c000 { 588 #address-cells = <1>; 589 #size-cells = <0>; 590 compatible = "st,stm32-timers"; 591 reg = <0x4c00c000 0x400>; 592 clocks = <&rcc TIM17_K>; 593 clock-names = "int"; 594 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 595 status = "disabled"; 596 }; 597 598 lptimer2: timer@50021000 { 599 #address-cells = <1>; 600 #size-cells = <0>; 601 compatible = "st,stm32-lptimer"; 602 reg = <0x50021000 0x400>; 603 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&rcc LPTIM2_K>; 605 clock-names = "mux"; 606 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 607 status = "disabled"; 608 }; 609 610 lptimer3: timer@50022000 { 611 #address-cells = <1>; 612 #size-cells = <0>; 613 compatible = "st,stm32-lptimer"; 614 reg = <0x50022000 0x400>; 615 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&rcc LPTIM3_K>; 617 clock-names = "mux"; 618 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 619 status = "disabled"; 620 621 counter { 622 compatible = "st,stm32-lptimer-counter"; 623 status = "disabled"; 624 }; 625 }; 626 627 vrefbuf: vrefbuf@50025000 { 628 compatible = "st,stm32mp13-vrefbuf"; 629 reg = <0x50025000 0x8>; 630 regulator-name = "vrefbuf"; 631 regulator-min-microvolt = <1650000>; 632 regulator-max-microvolt = <2500000>; 633 clocks = <&rcc VREF>; 634 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 635 status = "disabled"; 636 }; 637 638 hash: hash@54003000 { 639 compatible = "st,stm32mp13-hash"; 640 reg = <0x54003000 0x400>; 641 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&rcc HASH1>; 643 resets = <&rcc HASH1_R>; 644 access-controllers = <&etzpc STM32MP1_ETZPC_HASH_ID>; 645 status = "disabled"; 646 }; 647 648 rng: rng@54004000 { 649 compatible = "st,stm32mp13-rng"; 650 reg = <0x54004000 0x400>; 651 clocks = <&rcc RNG1_K>; 652 resets = <&rcc RNG1_R>; 653 access-controllers = <&etzpc STM32MP1_ETZPC_RNG_ID>; 654 status = "disabled"; 655 }; 656 657 iwdg1: watchdog@5c003000 { 658 compatible = "st,stm32mp1-iwdg"; 659 reg = <0x5C003000 0x400>; 660 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 662 clock-names = "pclk", "lsi"; 663 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 664 status = "disabled"; 665 }; 666 667 stgen: stgen@5c008000 { 668 compatible = "st,stm32-stgen"; 669 reg = <0x5C008000 0x1000>; 670 access-controllers = <&etzpc STM32MP1_ETZPC_STGENC_ID>; 671 }; 672 }; 673 }; 674}; 675