1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/clock/stm32mp13-clksrc.h> 9#include <dt-bindings/firewall/stm32mp13-etzpc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 12#include <dt-bindings/reset/stm32mp13-resets.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 compatible = "arm,cortex-a7"; 24 device_type = "cpu"; 25 reg = <0>; 26 }; 27 }; 28 29 hse_monitor: hse-monitor { 30 compatible = "st,freq-monitor"; 31 counter = <&lptimer3 1 1 0 0>; 32 status = "disabled"; 33 }; 34 35 intc: interrupt-controller@a0021000 { 36 compatible = "arm,cortex-a7-gic"; 37 #interrupt-cells = <3>; 38 interrupt-controller; 39 reg = <0xa0021000 0x1000>, 40 <0xa0022000 0x2000>; 41 }; 42 43 psci { 44 compatible = "arm,psci-1.0"; 45 method = "smc"; 46 }; 47 48 clocks { 49 clk_hse: clk-hse { 50 #clock-cells = <0>; 51 compatible = "fixed-clock"; 52 clock-frequency = <24000000>; 53 }; 54 55 clk_hsi: clk-hsi { 56 #clock-cells = <0>; 57 compatible = "fixed-clock"; 58 clock-frequency = <64000000>; 59 }; 60 61 clk_lse: clk-lse { 62 #clock-cells = <0>; 63 compatible = "fixed-clock"; 64 clock-frequency = <32768>; 65 }; 66 67 clk_lsi: clk-lsi { 68 #clock-cells = <0>; 69 compatible = "fixed-clock"; 70 clock-frequency = <32000>; 71 }; 72 73 clk_csi: clk-csi { 74 #clock-cells = <0>; 75 compatible = "fixed-clock"; 76 clock-frequency = <4000000>; 77 }; 78 79 clk_i2sin: clk-i2sin { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <19000000>; 83 }; 84 85 }; 86 87 sdmmc1_io: sdmmc1_io { 88 compatible = "st,stm32mp13-iod"; 89 regulator-name = "sdmmc1_io"; 90 regulator-always-on; 91 }; 92 93 sdmmc2_io: sdmmc2_io { 94 compatible = "st,stm32mp13-iod"; 95 regulator-name = "sdmmc2_io"; 96 regulator-always-on; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 interrupt-parent = <&intc>; 104 ranges; 105 106 usart3: serial@4000f000 { 107 compatible = "st,stm32h7-uart"; 108 reg = <0x4000f000 0x400>; 109 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&rcc USART3_K>; 111 resets = <&rcc USART3_R>; 112 status = "disabled"; 113 }; 114 115 uart4: serial@40010000 { 116 compatible = "st,stm32h7-uart"; 117 reg = <0x40010000 0x400>; 118 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&rcc UART4_K>; 120 resets = <&rcc UART4_R>; 121 status = "disabled"; 122 }; 123 124 uart5: serial@40011000 { 125 compatible = "st,stm32h7-uart"; 126 reg = <0x40011000 0x400>; 127 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 128 clocks = <&rcc UART5_K>; 129 resets = <&rcc UART5_R>; 130 status = "disabled"; 131 }; 132 133 uart7: serial@40018000 { 134 compatible = "st,stm32h7-uart"; 135 reg = <0x40018000 0x400>; 136 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&rcc UART7_K>; 138 resets = <&rcc UART7_R>; 139 status = "disabled"; 140 }; 141 142 uart8: serial@40019000 { 143 compatible = "st,stm32h7-uart"; 144 reg = <0x40019000 0x400>; 145 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&rcc UART8_K>; 147 resets = <&rcc UART8_R>; 148 status = "disabled"; 149 }; 150 151 usart6: serial@44003000 { 152 compatible = "st,stm32h7-uart"; 153 reg = <0x44003000 0x400>; 154 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&rcc USART6_K>; 156 resets = <&rcc USART6_R>; 157 status = "disabled"; 158 }; 159 160 rcc: rcc@50000000 { 161 compatible = "st,stm32mp13-rcc", "syscon"; 162 reg = <0x50000000 0x1000>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 #clock-cells = <1>; 166 #reset-cells = <1>; 167 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, <&clk_lsi>, <&clk_csi>, <&clk_i2sin>; 168 clock-names = "clk-hse", "clk-hsi", "clk-lse", "clk-lsi", "clk-csi", "clk-i2sin"; 169 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 170 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 171 secure-interrupt-names = "wakeup"; 172 }; 173 174 pwr_regulators: pwr@50001000 { 175 compatible = "st,stm32mp1,pwr-reg"; 176 reg = <0x50001000 0x10>; 177 178 reg11: reg11 { 179 regulator-name = "reg11"; 180 regulator-min-microvolt = <1100000>; 181 regulator-max-microvolt = <1100000>; 182 }; 183 184 reg18: reg18 { 185 regulator-name = "reg18"; 186 regulator-min-microvolt = <1800000>; 187 regulator-max-microvolt = <1800000>; 188 }; 189 190 usb33: usb33 { 191 regulator-name = "usb33"; 192 regulator-min-microvolt = <3300000>; 193 regulator-max-microvolt = <3300000>; 194 }; 195 }; 196 197 pwr_irq: pwr@50001010 { 198 compatible = "st,stm32mp1,pwr-irq"; 199 status = "disabled"; 200 }; 201 202 syscfg: syscon@50020000 { 203 compatible = "st,stm32mp157-syscfg", "syscon"; 204 reg = <0x50020000 0x400>; 205 }; 206 207 iwdg2: watchdog@5a002000 { 208 compatible = "st,stm32mp1-iwdg"; 209 reg = <0x5a002000 0x400>; 210 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 212 clock-names = "pclk", "lsi"; 213 status = "disabled"; 214 }; 215 216 rtc: rtc@5c004000 { 217 compatible = "st,stm32mp13-rtc"; 218 reg = <0x5c004000 0x400>; 219 clocks = <&rcc RTCAPB>, <&rcc RTC>; 220 clock-names = "pclk", "rtc_ck"; 221 status = "disabled"; 222 }; 223 224 bsec: efuse@5c005000 { 225 compatible = "st,stm32mp13-bsec"; 226 reg = <0x5c005000 0x400>; 227 #address-cells = <1>; 228 #size-cells = <1>; 229 230 cfg0_otp: cfg0_otp@0 { 231 reg = <0x0 0x2>; 232 }; 233 part_number_otp: part_number_otp@4 { 234 reg = <0x4 0x2>; 235 bits = <0 12>; 236 }; 237 monotonic_otp: monotonic_otp@10 { 238 reg = <0x10 0x4>; 239 }; 240 nand_otp: cfg9_otp@24 { 241 reg = <0x24 0x4>; 242 }; 243 uid_otp: uid_otp@34 { 244 reg = <0x34 0xc>; 245 }; 246 hw2_otp: hw2_otp@48 { 247 reg = <0x48 0x4>; 248 }; 249 ts_cal1: calib@5c { 250 reg = <0x5c 0x2>; 251 }; 252 ts_cal2: calib@5e { 253 reg = <0x5e 0x2>; 254 }; 255 pkh_otp: pkh_otp@60 { 256 reg = <0x60 0x20>; 257 }; 258 ethernet_mac1_address: mac1@e4 { 259 reg = <0xe4 0xc>; 260 st,non-secure-otp; 261 }; 262 oem_enc_key: oem_enc_key@170 { 263 reg = <0x170 0x10>; 264 }; 265 }; 266 267 tzc400: tzc@5c006000 { 268 compatible = "st,stm32mp1-tzc"; 269 reg = <0x5c006000 0x1000>; 270 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 271 st,mem-map = <0xc0000000 0x40000000>; 272 clocks = <&rcc TZC>; 273 }; 274 275 tamp: tamp@5c00a000 { 276 compatible = "st,stm32mp13-tamp"; 277 reg = <0x5c00a000 0x400>; 278 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&rcc RTCAPB>; 280 st,backup-zones = <10 5 17>; 281 }; 282 283 pinctrl: pin-controller@50002000 { 284 #address-cells = <1>; 285 #size-cells = <1>; 286 compatible = "st,stm32mp135-pinctrl"; 287 ranges = <0 0x50002000 0x8400>; 288 pins-are-numbered; 289 290 gpioa: gpio@50002000 { 291 gpio-controller; 292 #gpio-cells = <2>; 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 clocks = <&rcc GPIOA>; 296 reg = <0x0 0x400>; 297 st,bank-name = "GPIOA"; 298 ngpios = <16>; 299 gpio-ranges = <&pinctrl 0 0 16>; 300 }; 301 302 gpiob: gpio@50003000 { 303 gpio-controller; 304 #gpio-cells = <2>; 305 interrupt-controller; 306 #interrupt-cells = <2>; 307 clocks = <&rcc GPIOB>; 308 reg = <0x1000 0x400>; 309 st,bank-name = "GPIOB"; 310 ngpios = <16>; 311 gpio-ranges = <&pinctrl 0 16 16>; 312 }; 313 314 gpioc: gpio@50004000 { 315 gpio-controller; 316 #gpio-cells = <2>; 317 interrupt-controller; 318 #interrupt-cells = <2>; 319 clocks = <&rcc GPIOC>; 320 reg = <0x2000 0x400>; 321 st,bank-name = "GPIOC"; 322 ngpios = <16>; 323 gpio-ranges = <&pinctrl 0 32 16>; 324 }; 325 326 gpiod: gpio@50005000 { 327 gpio-controller; 328 #gpio-cells = <2>; 329 interrupt-controller; 330 #interrupt-cells = <2>; 331 clocks = <&rcc GPIOD>; 332 reg = <0x3000 0x400>; 333 st,bank-name = "GPIOD"; 334 ngpios = <16>; 335 gpio-ranges = <&pinctrl 0 48 16>; 336 }; 337 338 gpioe: gpio@50006000 { 339 gpio-controller; 340 #gpio-cells = <2>; 341 interrupt-controller; 342 #interrupt-cells = <2>; 343 clocks = <&rcc GPIOE>; 344 reg = <0x4000 0x400>; 345 st,bank-name = "GPIOE"; 346 ngpios = <16>; 347 gpio-ranges = <&pinctrl 0 64 16>; 348 }; 349 350 gpiof: gpio@50007000 { 351 gpio-controller; 352 #gpio-cells = <2>; 353 interrupt-controller; 354 #interrupt-cells = <2>; 355 clocks = <&rcc GPIOF>; 356 reg = <0x5000 0x400>; 357 st,bank-name = "GPIOF"; 358 ngpios = <16>; 359 gpio-ranges = <&pinctrl 0 80 16>; 360 }; 361 362 gpiog: gpio@50008000 { 363 gpio-controller; 364 #gpio-cells = <2>; 365 interrupt-controller; 366 #interrupt-cells = <2>; 367 clocks = <&rcc GPIOG>; 368 reg = <0x6000 0x400>; 369 st,bank-name = "GPIOG"; 370 ngpios = <16>; 371 gpio-ranges = <&pinctrl 0 96 16>; 372 }; 373 374 gpioh: gpio@50009000 { 375 gpio-controller; 376 #gpio-cells = <2>; 377 interrupt-controller; 378 #interrupt-cells = <2>; 379 clocks = <&rcc GPIOH>; 380 reg = <0x7000 0x400>; 381 st,bank-name = "GPIOH"; 382 ngpios = <15>; 383 gpio-ranges = <&pinctrl 0 112 15>; 384 }; 385 386 gpioi: gpio@5000a000 { 387 gpio-controller; 388 #gpio-cells = <2>; 389 interrupt-controller; 390 #interrupt-cells = <2>; 391 clocks = <&rcc GPIOI>; 392 reg = <0x8000 0x400>; 393 st,bank-name = "GPIOI"; 394 ngpios = <8>; 395 gpio-ranges = <&pinctrl 0 128 8>; 396 }; 397 }; 398 399 etzpc: etzpc@5c007000 { 400 compatible = "st,stm32-etzpc", "simple-bus"; 401 reg = <0x5C007000 0x400>; 402 clocks = <&rcc TZPC>; 403 #address-cells = <1>; 404 #size-cells = <1>; 405 #access-controller-cells = <1>; 406 407 adc_2: adc@48004000 { 408 reg = <0x48004000 0x400>; 409 compatible = "st,stm32mp13-adc-core"; 410 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 412 clock-names = "bus", "adc"; 413 interrupt-controller; 414 #interrupt-cells = <1>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 access-controllers = <&etzpc STM32MP1_ETZPC_ADC2_ID>; 418 status = "disabled"; 419 420 adc2: adc@0 { 421 compatible = "st,stm32mp13-adc"; 422 reg = <0x0>; 423 #io-channel-cells = <1>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 interrupt-parent = <&adc_2>; 427 interrupts = <0>; 428 status = "disabled"; 429 430 channel@13 { 431 reg = <13>; 432 label = "vrefint"; 433 }; 434 435 channel@14 { 436 reg = <14>; 437 label = "vddcore"; 438 }; 439 440 channel@16 { 441 reg = <16>; 442 label = "vddcpu"; 443 }; 444 445 channel@17 { 446 reg = <17>; 447 label = "vddq_ddr"; 448 }; 449 }; 450 }; 451 452 usart1: serial@4c000000 { 453 compatible = "st,stm32h7-uart"; 454 reg = <0x4c000000 0x400>; 455 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&rcc USART1_K>; 457 resets = <&rcc USART1_R>; 458 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 459 status = "disabled"; 460 }; 461 462 usart2: serial@4c001000 { 463 compatible = "st,stm32h7-uart"; 464 reg = <0x4c001000 0x400>; 465 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&rcc USART2_K>; 467 resets = <&rcc USART2_R>; 468 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 469 status = "disabled"; 470 }; 471 472 i2c3: i2c@4c004000 { 473 compatible = "st,stm32mp13-i2c"; 474 reg = <0x4c004000 0x400>; 475 clocks = <&rcc I2C3_K>; 476 resets = <&rcc I2C3_R>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 st,syscfg-fmp = <&syscfg 0x4 0x4>; 480 i2c-analog-filter; 481 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 482 status = "disabled"; 483 }; 484 485 i2c4: i2c@4c005000 { 486 compatible = "st,stm32mp13-i2c"; 487 reg = <0x4c005000 0x400>; 488 clocks = <&rcc I2C4_K>; 489 resets = <&rcc I2C4_R>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 st,syscfg-fmp = <&syscfg 0x4 0x8>; 493 i2c-analog-filter; 494 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 495 status = "disabled"; 496 }; 497 498 i2c5: i2c@4c006000 { 499 compatible = "st,stm32mp13-i2c"; 500 reg = <0x4c006000 0x400>; 501 clocks = <&rcc I2C5_K>; 502 resets = <&rcc I2C5_R>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 st,syscfg-fmp = <&syscfg 0x4 0x10>; 506 i2c-analog-filter; 507 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 508 status = "disabled"; 509 }; 510 511 timers12: timer@4c007000 { 512 #address-cells = <1>; 513 #size-cells = <0>; 514 compatible = "st,stm32-timers"; 515 reg = <0x4c007000 0x400>; 516 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&rcc TIM12_K>; 518 clock-names = "int"; 519 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 520 status = "disabled"; 521 522 counter { 523 compatible = "st,stm32-timer-counter"; 524 status = "disabled"; 525 }; 526 }; 527 528 timers13: timer@4c008000 { 529 #address-cells = <1>; 530 #size-cells = <0>; 531 compatible = "st,stm32-timers"; 532 reg = <0x4c008000 0x400>; 533 clocks = <&rcc TIM13_K>; 534 clock-names = "int"; 535 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 536 status = "disabled"; 537 }; 538 539 timers14: timer@4c009000 { 540 #address-cells = <1>; 541 #size-cells = <0>; 542 compatible = "st,stm32-timers"; 543 reg = <0x4c009000 0x400>; 544 clocks = <&rcc TIM14_K>; 545 clock-names = "int"; 546 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 547 status = "disabled"; 548 }; 549 550 timers15: timer@4c00a000 { 551 #address-cells = <1>; 552 #size-cells = <0>; 553 compatible = "st,stm32-timers"; 554 reg = <0x4c00a000 0x400>; 555 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&rcc TIM15_K>; 557 clock-names = "int"; 558 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 559 status = "disabled"; 560 561 counter { 562 compatible = "st,stm32-timer-counter"; 563 status = "disabled"; 564 }; 565 }; 566 567 timers16: timer@4c00b000 { 568 #address-cells = <1>; 569 #size-cells = <0>; 570 compatible = "st,stm32-timers"; 571 reg = <0x4c00b000 0x400>; 572 clocks = <&rcc TIM16_K>; 573 clock-names = "int"; 574 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 575 status = "disabled"; 576 }; 577 578 timers17: timer@4c00c000 { 579 #address-cells = <1>; 580 #size-cells = <0>; 581 compatible = "st,stm32-timers"; 582 reg = <0x4c00c000 0x400>; 583 clocks = <&rcc TIM17_K>; 584 clock-names = "int"; 585 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 586 status = "disabled"; 587 }; 588 589 lptimer2: timer@50021000 { 590 #address-cells = <1>; 591 #size-cells = <0>; 592 compatible = "st,stm32-lptimer"; 593 reg = <0x50021000 0x400>; 594 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&rcc LPTIM2_K>; 596 clock-names = "mux"; 597 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 598 status = "disabled"; 599 }; 600 601 lptimer3: timer@50022000 { 602 #address-cells = <1>; 603 #size-cells = <0>; 604 compatible = "st,stm32-lptimer"; 605 reg = <0x50022000 0x400>; 606 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&rcc LPTIM3_K>; 608 clock-names = "mux"; 609 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 610 status = "disabled"; 611 612 counter { 613 compatible = "st,stm32-lptimer-counter"; 614 status = "disabled"; 615 }; 616 }; 617 618 vrefbuf: vrefbuf@50025000 { 619 compatible = "st,stm32mp13-vrefbuf"; 620 reg = <0x50025000 0x8>; 621 regulator-name = "vrefbuf"; 622 regulator-min-microvolt = <1650000>; 623 regulator-max-microvolt = <2500000>; 624 clocks = <&rcc VREF>; 625 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 626 status = "disabled"; 627 }; 628 629 hash: hash@54003000 { 630 compatible = "st,stm32mp13-hash"; 631 reg = <0x54003000 0x400>; 632 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&rcc HASH1>; 634 resets = <&rcc HASH1_R>; 635 access-controllers = <&etzpc STM32MP1_ETZPC_HASH_ID>; 636 status = "disabled"; 637 }; 638 639 rng: rng@54004000 { 640 compatible = "st,stm32mp13-rng"; 641 reg = <0x54004000 0x400>; 642 clocks = <&rcc RNG1_K>; 643 resets = <&rcc RNG1_R>; 644 access-controllers = <&etzpc STM32MP1_ETZPC_RNG_ID>; 645 status = "disabled"; 646 }; 647 648 iwdg1: watchdog@5c003000 { 649 compatible = "st,stm32mp1-iwdg"; 650 reg = <0x5C003000 0x400>; 651 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 653 clock-names = "pclk", "lsi"; 654 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 655 status = "disabled"; 656 }; 657 658 stgen: stgen@5c008000 { 659 compatible = "st,stm32-stgen"; 660 reg = <0x5C008000 0x1000>; 661 access-controllers = <&etzpc STM32MP1_ETZPC_STGENC_ID>; 662 }; 663 }; 664 }; 665}; 666