1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2025 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/clock/stm32mp13-clksrc.h> 9#include <dt-bindings/firewall/stm32mp13-etzpc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 12#include <dt-bindings/reset/stm32mp13-resets.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 compatible = "arm,cortex-a7"; 24 device_type = "cpu"; 25 reg = <0>; 26 clocks = <&rcc CK_MPU>; 27 clock-names = "cpu"; 28 operating-points-v2 = <&cpu0_opp_table>; 29 nvmem-cells = <&part_number_otp>; 30 nvmem-cell-names = "part_number"; 31 }; 32 }; 33 34 cpu0_opp_table: cpu0-opp-table { 35 compatible = "operating-points-v2"; 36 37 /* Non‑overdrive OPP mission profile */ 38 opp-650000000 { 39 opp-hz = /bits/ 64 <650000000>; 40 opp-microvolt = <1250000>; 41 opp-supported-hw = <0x3>; 42 st,opp-default; 43 }; 44 45 /* Overdrive OPP: 10‑year life activity @100% activity rate */ 46 opp-900000000 { 47 opp-hz = /bits/ 64 <900000000>; 48 opp-microvolt = <1350000>; 49 opp-supported-hw = <0x2>; 50 st,opp-default; 51 }; 52 53 /* Overdrive OPP: 10‑year life activity @25% activity rate */ 54 opp-1000000000 { 55 opp-hz = /bits/ 64 <1000000000>; 56 opp-microvolt = <1350000>; 57 opp-supported-hw = <0x2>; 58 }; 59 }; 60 61 hse_monitor: hse-monitor { 62 compatible = "st,freq-monitor"; 63 counter = <&lptimer3 1 1 0 0>; 64 status = "disabled"; 65 }; 66 67 intc: interrupt-controller@a0021000 { 68 compatible = "arm,cortex-a7-gic"; 69 #interrupt-cells = <3>; 70 interrupt-controller; 71 reg = <0xa0021000 0x1000>, 72 <0xa0022000 0x2000>; 73 }; 74 75 psci { 76 compatible = "arm,psci-1.0"; 77 method = "smc"; 78 }; 79 80 clocks { 81 clk_hse: clk-hse { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <24000000>; 85 }; 86 87 clk_hsi: clk-hsi { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <64000000>; 91 }; 92 93 clk_lse: clk-lse { 94 #clock-cells = <0>; 95 compatible = "fixed-clock"; 96 clock-frequency = <32768>; 97 }; 98 99 clk_lsi: clk-lsi { 100 #clock-cells = <0>; 101 compatible = "fixed-clock"; 102 clock-frequency = <32000>; 103 }; 104 105 clk_csi: clk-csi { 106 #clock-cells = <0>; 107 compatible = "fixed-clock"; 108 clock-frequency = <4000000>; 109 }; 110 111 clk_i2sin: clk-i2sin { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 clock-frequency = <19000000>; 115 }; 116 117 }; 118 119 sdmmc1_io: sdmmc1_io { 120 compatible = "st,stm32mp13-iod"; 121 regulator-name = "sdmmc1_io"; 122 regulator-always-on; 123 }; 124 125 sdmmc2_io: sdmmc2_io { 126 compatible = "st,stm32mp13-iod"; 127 regulator-name = "sdmmc2_io"; 128 regulator-always-on; 129 }; 130 131 soc { 132 compatible = "simple-bus"; 133 #address-cells = <1>; 134 #size-cells = <1>; 135 interrupt-parent = <&intc>; 136 ranges; 137 138 usart3: serial@4000f000 { 139 compatible = "st,stm32h7-uart"; 140 reg = <0x4000f000 0x400>; 141 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&rcc USART3_K>; 143 resets = <&rcc USART3_R>; 144 status = "disabled"; 145 }; 146 147 uart4: serial@40010000 { 148 compatible = "st,stm32h7-uart"; 149 reg = <0x40010000 0x400>; 150 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 151 clocks = <&rcc UART4_K>; 152 resets = <&rcc UART4_R>; 153 status = "disabled"; 154 }; 155 156 uart5: serial@40011000 { 157 compatible = "st,stm32h7-uart"; 158 reg = <0x40011000 0x400>; 159 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&rcc UART5_K>; 161 resets = <&rcc UART5_R>; 162 status = "disabled"; 163 }; 164 165 i2c1: i2c@40012000 { 166 compatible = "st,stm32mp13-i2c"; 167 reg = <0x40012000 0x400>; 168 clocks = <&rcc I2C1_K>; 169 resets = <&rcc I2C1_R>; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 st,syscfg-fmp = <&syscfg 0x4 0x1>; 173 i2c-analog-filter; 174 status = "disabled"; 175 }; 176 177 i2c2: i2c@40013000 { 178 compatible = "st,stm32mp13-i2c"; 179 reg = <0x40013000 0x400>; 180 clocks = <&rcc I2C2_K>; 181 resets = <&rcc I2C2_R>; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 st,syscfg-fmp = <&syscfg 0x4 0x2>; 185 i2c-analog-filter; 186 status = "disabled"; 187 }; 188 189 uart7: serial@40018000 { 190 compatible = "st,stm32h7-uart"; 191 reg = <0x40018000 0x400>; 192 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&rcc UART7_K>; 194 resets = <&rcc UART7_R>; 195 status = "disabled"; 196 }; 197 198 uart8: serial@40019000 { 199 compatible = "st,stm32h7-uart"; 200 reg = <0x40019000 0x400>; 201 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&rcc UART8_K>; 203 resets = <&rcc UART8_R>; 204 status = "disabled"; 205 }; 206 207 usart6: serial@44003000 { 208 compatible = "st,stm32h7-uart"; 209 reg = <0x44003000 0x400>; 210 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&rcc USART6_K>; 212 resets = <&rcc USART6_R>; 213 status = "disabled"; 214 }; 215 216 rcc: rcc@50000000 { 217 compatible = "st,stm32mp13-rcc", "syscon"; 218 reg = <0x50000000 0x1000>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 #clock-cells = <1>; 222 #reset-cells = <1>; 223 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, <&clk_lsi>, <&clk_csi>, <&clk_i2sin>; 224 clock-names = "clk-hse", "clk-hsi", "clk-lse", "clk-lsi", "clk-csi", "clk-i2sin"; 225 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 226 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 227 secure-interrupt-names = "wakeup"; 228 }; 229 230 pwr_regulators: pwr@50001000 { 231 compatible = "st,stm32mp1-pwr-reg"; 232 reg = <0x50001000 0x10>; 233 234 reg11: reg11 { 235 regulator-name = "reg11"; 236 regulator-min-microvolt = <1100000>; 237 regulator-max-microvolt = <1100000>; 238 }; 239 240 reg18: reg18 { 241 regulator-name = "reg18"; 242 regulator-min-microvolt = <1800000>; 243 regulator-max-microvolt = <1800000>; 244 }; 245 246 usb33: usb33 { 247 regulator-name = "usb33"; 248 regulator-min-microvolt = <3300000>; 249 regulator-max-microvolt = <3300000>; 250 }; 251 }; 252 253 pwr_irq: pwr@50001010 { 254 compatible = "st,stm32mp1,pwr-irq"; 255 status = "disabled"; 256 }; 257 258 exti: interrupt-controller@5000d000 { 259 compatible = "st,stm32mp1-exti"; 260 interrupt-controller; 261 #interrupt-cells = <2>; 262 reg = <0x5000d000 0x400>; 263 interrupts-extended = 264 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 265 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 266 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 267 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 268 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 269 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 270 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 271 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 272 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 273 <&intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 274 <&intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 275 <&intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 276 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 277 <&intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 278 <&intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 279 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 280 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 281 <0>, 282 <&intc GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 283 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 284 <0>, /* EXTI_20 */ 285 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 286 <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 287 <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 288 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 289 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 290 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 291 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 292 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 293 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 294 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 295 <&intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 296 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 297 <&intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 298 <0>, 299 <0>, 300 <0>, 301 <0>, 302 <0>, 303 <0>, 304 <0>, /* EXTI_40 */ 305 <0>, 306 <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 307 <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 308 <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 309 <0>, 310 <0>, 311 <&intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 312 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 313 <0>, 314 <&intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 315 <0>, 316 <&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 317 <&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 318 <0>, 319 <0>, 320 <0>, 321 <0>, 322 <0>, 323 <0>, 324 <0>, /* EXTI_60 */ 325 <0>, 326 <0>, 327 <0>, 328 <0>, 329 <0>, 330 <0>, 331 <0>, 332 <&intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 333 <0>, 334 <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 335 }; 336 337 syscfg: syscon@50020000 { 338 compatible = "st,stm32mp157-syscfg", "syscon"; 339 reg = <0x50020000 0x400>; 340 }; 341 342 iwdg2: watchdog@5a002000 { 343 compatible = "st,stm32mp1-iwdg"; 344 reg = <0x5a002000 0x400>; 345 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 347 clock-names = "pclk", "lsi"; 348 status = "disabled"; 349 }; 350 351 rtc: rtc@5c004000 { 352 compatible = "st,stm32mp13-rtc"; 353 reg = <0x5c004000 0x400>; 354 clocks = <&rcc RTCAPB>, <&rcc RTC>; 355 clock-names = "pclk", "rtc_ck"; 356 status = "disabled"; 357 }; 358 359 bsec: efuse@5c005000 { 360 compatible = "st,stm32mp13-bsec"; 361 reg = <0x5c005000 0x400>; 362 #address-cells = <1>; 363 #size-cells = <1>; 364 365 cfg0_otp: cfg0_otp@0 { 366 reg = <0x0 0x2>; 367 }; 368 part_number_otp: part_number_otp@4 { 369 reg = <0x4 0x2>; 370 bits = <0 12>; 371 }; 372 monotonic_otp: monotonic_otp@10 { 373 reg = <0x10 0x4>; 374 }; 375 nand_otp: cfg9_otp@24 { 376 reg = <0x24 0x4>; 377 }; 378 uid_otp: uid_otp@34 { 379 reg = <0x34 0xc>; 380 }; 381 hw2_otp: hw2_otp@48 { 382 reg = <0x48 0x4>; 383 }; 384 ts_cal1: calib@5c { 385 reg = <0x5c 0x2>; 386 }; 387 ts_cal2: calib@5e { 388 reg = <0x5e 0x2>; 389 }; 390 pkh_otp: pkh_otp@60 { 391 reg = <0x60 0x20>; 392 }; 393 ethernet_mac1_address: mac1@e4 { 394 reg = <0xe4 0xc>; 395 st,non-secure-otp; 396 }; 397 oem_enc_key: oem_enc_key@170 { 398 reg = <0x170 0x10>; 399 }; 400 }; 401 402 tzc400: tzc@5c006000 { 403 compatible = "st,stm32mp1-tzc"; 404 reg = <0x5c006000 0x1000>; 405 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 406 st,mem-map = <0xc0000000 0x40000000>; 407 clocks = <&rcc TZC>; 408 }; 409 410 tamp: tamp@5c00a000 { 411 compatible = "st,stm32mp13-tamp"; 412 reg = <0x5c00a000 0x400>; 413 interrupts-extended = <&exti 18 IRQ_TYPE_EDGE_RISING>; 414 clocks = <&rcc RTCAPB>; 415 st,backup-zones = <10 5 17>; 416 }; 417 418 pinctrl: pin-controller@50002000 { 419 #address-cells = <1>; 420 #size-cells = <1>; 421 compatible = "st,stm32mp135-pinctrl"; 422 ranges = <0 0x50002000 0x8400>; 423 424 gpioa: gpio@50002000 { 425 gpio-controller; 426 #gpio-cells = <2>; 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 #access-controller-cells = <1>; 430 clocks = <&rcc GPIOA>; 431 reg = <0x0 0x400>; 432 st,bank-name = "GPIOA"; 433 ngpios = <16>; 434 gpio-ranges = <&pinctrl 0 0 16>; 435 }; 436 437 gpiob: gpio@50003000 { 438 gpio-controller; 439 #gpio-cells = <2>; 440 interrupt-controller; 441 #interrupt-cells = <2>; 442 #access-controller-cells = <1>; 443 clocks = <&rcc GPIOB>; 444 reg = <0x1000 0x400>; 445 st,bank-name = "GPIOB"; 446 ngpios = <16>; 447 gpio-ranges = <&pinctrl 0 16 16>; 448 }; 449 450 gpioc: gpio@50004000 { 451 gpio-controller; 452 #gpio-cells = <2>; 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 #access-controller-cells = <1>; 456 clocks = <&rcc GPIOC>; 457 reg = <0x2000 0x400>; 458 st,bank-name = "GPIOC"; 459 ngpios = <16>; 460 gpio-ranges = <&pinctrl 0 32 16>; 461 }; 462 463 gpiod: gpio@50005000 { 464 gpio-controller; 465 #gpio-cells = <2>; 466 interrupt-controller; 467 #interrupt-cells = <2>; 468 #access-controller-cells = <1>; 469 clocks = <&rcc GPIOD>; 470 reg = <0x3000 0x400>; 471 st,bank-name = "GPIOD"; 472 ngpios = <16>; 473 gpio-ranges = <&pinctrl 0 48 16>; 474 }; 475 476 gpioe: gpio@50006000 { 477 gpio-controller; 478 #gpio-cells = <2>; 479 interrupt-controller; 480 #interrupt-cells = <2>; 481 #access-controller-cells = <1>; 482 clocks = <&rcc GPIOE>; 483 reg = <0x4000 0x400>; 484 st,bank-name = "GPIOE"; 485 ngpios = <16>; 486 gpio-ranges = <&pinctrl 0 64 16>; 487 }; 488 489 gpiof: gpio@50007000 { 490 gpio-controller; 491 #gpio-cells = <2>; 492 interrupt-controller; 493 #interrupt-cells = <2>; 494 #access-controller-cells = <1>; 495 clocks = <&rcc GPIOF>; 496 reg = <0x5000 0x400>; 497 st,bank-name = "GPIOF"; 498 ngpios = <16>; 499 gpio-ranges = <&pinctrl 0 80 16>; 500 }; 501 502 gpiog: gpio@50008000 { 503 gpio-controller; 504 #gpio-cells = <2>; 505 interrupt-controller; 506 #interrupt-cells = <2>; 507 #access-controller-cells = <1>; 508 clocks = <&rcc GPIOG>; 509 reg = <0x6000 0x400>; 510 st,bank-name = "GPIOG"; 511 ngpios = <16>; 512 gpio-ranges = <&pinctrl 0 96 16>; 513 }; 514 515 gpioh: gpio@50009000 { 516 gpio-controller; 517 #gpio-cells = <2>; 518 interrupt-controller; 519 #interrupt-cells = <2>; 520 #access-controller-cells = <1>; 521 clocks = <&rcc GPIOH>; 522 reg = <0x7000 0x400>; 523 st,bank-name = "GPIOH"; 524 ngpios = <15>; 525 gpio-ranges = <&pinctrl 0 112 15>; 526 }; 527 528 gpioi: gpio@5000a000 { 529 gpio-controller; 530 #gpio-cells = <2>; 531 interrupt-controller; 532 #interrupt-cells = <2>; 533 #access-controller-cells = <1>; 534 clocks = <&rcc GPIOI>; 535 reg = <0x8000 0x400>; 536 st,bank-name = "GPIOI"; 537 ngpios = <8>; 538 gpio-ranges = <&pinctrl 0 128 8>; 539 }; 540 }; 541 542 etzpc: etzpc@5c007000 { 543 compatible = "st,stm32-etzpc", "simple-bus"; 544 reg = <0x5C007000 0x400>; 545 clocks = <&rcc TZPC>; 546 #address-cells = <1>; 547 #size-cells = <1>; 548 #access-controller-cells = <1>; 549 550 adc_2: adc@48004000 { 551 reg = <0x48004000 0x400>; 552 compatible = "st,stm32mp13-adc-core"; 553 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 555 clock-names = "bus", "adc"; 556 interrupt-controller; 557 #interrupt-cells = <1>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 access-controllers = <&etzpc STM32MP1_ETZPC_ADC2_ID>; 561 status = "disabled"; 562 563 adc2: adc@0 { 564 compatible = "st,stm32mp13-adc"; 565 reg = <0x0>; 566 #io-channel-cells = <1>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 interrupt-parent = <&adc_2>; 570 interrupts = <0>; 571 status = "disabled"; 572 573 channel@13 { 574 reg = <13>; 575 label = "vrefint"; 576 }; 577 578 channel@14 { 579 reg = <14>; 580 label = "vddcore"; 581 }; 582 583 channel@16 { 584 reg = <16>; 585 label = "vddcpu"; 586 }; 587 588 channel@17 { 589 reg = <17>; 590 label = "vddq_ddr"; 591 }; 592 }; 593 }; 594 595 usart1: serial@4c000000 { 596 compatible = "st,stm32h7-uart"; 597 reg = <0x4c000000 0x400>; 598 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&rcc USART1_K>; 600 resets = <&rcc USART1_R>; 601 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 602 status = "disabled"; 603 }; 604 605 usart2: serial@4c001000 { 606 compatible = "st,stm32h7-uart"; 607 reg = <0x4c001000 0x400>; 608 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&rcc USART2_K>; 610 resets = <&rcc USART2_R>; 611 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 612 status = "disabled"; 613 }; 614 615 i2c3: i2c@4c004000 { 616 compatible = "st,stm32mp13-i2c"; 617 reg = <0x4c004000 0x400>; 618 clocks = <&rcc I2C3_K>; 619 resets = <&rcc I2C3_R>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 st,syscfg-fmp = <&syscfg 0x4 0x4>; 623 i2c-analog-filter; 624 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 625 status = "disabled"; 626 }; 627 628 i2c4: i2c@4c005000 { 629 compatible = "st,stm32mp13-i2c"; 630 reg = <0x4c005000 0x400>; 631 clocks = <&rcc I2C4_K>; 632 resets = <&rcc I2C4_R>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 st,syscfg-fmp = <&syscfg 0x4 0x8>; 636 i2c-analog-filter; 637 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 638 status = "disabled"; 639 }; 640 641 i2c5: i2c@4c006000 { 642 compatible = "st,stm32mp13-i2c"; 643 reg = <0x4c006000 0x400>; 644 clocks = <&rcc I2C5_K>; 645 resets = <&rcc I2C5_R>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 st,syscfg-fmp = <&syscfg 0x4 0x10>; 649 i2c-analog-filter; 650 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 651 status = "disabled"; 652 }; 653 654 timers12: timer@4c007000 { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 compatible = "st,stm32-timers"; 658 reg = <0x4c007000 0x400>; 659 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&rcc TIM12_K>; 661 clock-names = "int"; 662 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 663 status = "disabled"; 664 665 counter { 666 compatible = "st,stm32-timer-counter"; 667 status = "disabled"; 668 }; 669 }; 670 671 timers13: timer@4c008000 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 compatible = "st,stm32-timers"; 675 reg = <0x4c008000 0x400>; 676 clocks = <&rcc TIM13_K>; 677 clock-names = "int"; 678 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 679 status = "disabled"; 680 }; 681 682 timers14: timer@4c009000 { 683 #address-cells = <1>; 684 #size-cells = <0>; 685 compatible = "st,stm32-timers"; 686 reg = <0x4c009000 0x400>; 687 clocks = <&rcc TIM14_K>; 688 clock-names = "int"; 689 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 690 status = "disabled"; 691 }; 692 693 timers15: timer@4c00a000 { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 compatible = "st,stm32-timers"; 697 reg = <0x4c00a000 0x400>; 698 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&rcc TIM15_K>; 700 clock-names = "int"; 701 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 702 status = "disabled"; 703 704 counter { 705 compatible = "st,stm32-timer-counter"; 706 status = "disabled"; 707 }; 708 }; 709 710 timers16: timer@4c00b000 { 711 #address-cells = <1>; 712 #size-cells = <0>; 713 compatible = "st,stm32-timers"; 714 reg = <0x4c00b000 0x400>; 715 clocks = <&rcc TIM16_K>; 716 clock-names = "int"; 717 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 718 status = "disabled"; 719 }; 720 721 timers17: timer@4c00c000 { 722 #address-cells = <1>; 723 #size-cells = <0>; 724 compatible = "st,stm32-timers"; 725 reg = <0x4c00c000 0x400>; 726 clocks = <&rcc TIM17_K>; 727 clock-names = "int"; 728 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 729 status = "disabled"; 730 }; 731 732 lptimer2: timer@50021000 { 733 #address-cells = <1>; 734 #size-cells = <0>; 735 compatible = "st,stm32-lptimer"; 736 reg = <0x50021000 0x400>; 737 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&rcc LPTIM2_K>; 739 clock-names = "mux"; 740 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 741 status = "disabled"; 742 }; 743 744 lptimer3: timer@50022000 { 745 #address-cells = <1>; 746 #size-cells = <0>; 747 compatible = "st,stm32-lptimer"; 748 reg = <0x50022000 0x400>; 749 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&rcc LPTIM3_K>; 751 clock-names = "mux"; 752 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 753 status = "disabled"; 754 755 counter { 756 compatible = "st,stm32-lptimer-counter"; 757 status = "disabled"; 758 }; 759 }; 760 761 vrefbuf: vrefbuf@50025000 { 762 compatible = "st,stm32mp13-vrefbuf"; 763 reg = <0x50025000 0x8>; 764 regulator-name = "vrefbuf"; 765 regulator-min-microvolt = <1650000>; 766 regulator-max-microvolt = <2500000>; 767 clocks = <&rcc VREF>; 768 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 769 status = "disabled"; 770 }; 771 772 hash: hash@54003000 { 773 compatible = "st,stm32mp13-hash"; 774 reg = <0x54003000 0x400>; 775 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&rcc HASH1>; 777 resets = <&rcc HASH1_R>; 778 access-controllers = <&etzpc STM32MP1_ETZPC_HASH_ID>; 779 status = "disabled"; 780 }; 781 782 rng: rng@54004000 { 783 compatible = "st,stm32mp13-rng"; 784 reg = <0x54004000 0x400>; 785 clocks = <&rcc RNG1_K>; 786 resets = <&rcc RNG1_R>; 787 access-controllers = <&etzpc STM32MP1_ETZPC_RNG_ID>; 788 status = "disabled"; 789 }; 790 791 iwdg1: watchdog@5c003000 { 792 compatible = "st,stm32mp1-iwdg"; 793 reg = <0x5C003000 0x400>; 794 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 796 clock-names = "pclk", "lsi"; 797 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 798 status = "disabled"; 799 }; 800 801 stgen: stgen@5c008000 { 802 compatible = "st,stm32-stgen"; 803 reg = <0x5C008000 0x1000>; 804 access-controllers = <&etzpc STM32MP1_ETZPC_STGENC_ID>; 805 }; 806 }; 807 }; 808}; 809