1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2022 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/clock/stm32mp13-clksrc.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/reset/stm32mp13-resets.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "arm,cortex-a7"; 22 device_type = "cpu"; 23 reg = <0>; 24 }; 25 }; 26 27 intc: interrupt-controller@a0021000 { 28 compatible = "arm,cortex-a7-gic"; 29 #interrupt-cells = <3>; 30 interrupt-controller; 31 reg = <0xa0021000 0x1000>, 32 <0xa0022000 0x2000>; 33 }; 34 35 psci { 36 compatible = "arm,psci-1.0"; 37 method = "smc"; 38 }; 39 40 clocks { 41 clk_hse: clk-hse { 42 #clock-cells = <0>; 43 compatible = "fixed-clock"; 44 clock-frequency = <24000000>; 45 }; 46 47 clk_hsi: clk-hsi { 48 #clock-cells = <0>; 49 compatible = "fixed-clock"; 50 clock-frequency = <64000000>; 51 }; 52 53 clk_lse: clk-lse { 54 #clock-cells = <0>; 55 compatible = "fixed-clock"; 56 clock-frequency = <32768>; 57 }; 58 59 clk_lsi: clk-lsi { 60 #clock-cells = <0>; 61 compatible = "fixed-clock"; 62 clock-frequency = <32000>; 63 }; 64 65 clk_csi: clk-csi { 66 #clock-cells = <0>; 67 compatible = "fixed-clock"; 68 clock-frequency = <4000000>; 69 }; 70 71 clk_i2sin: clk-i2sin { 72 #clock-cells = <0>; 73 compatible = "fixed-clock"; 74 clock-frequency = <19000000>; 75 }; 76 77 }; 78 79 soc { 80 compatible = "simple-bus"; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 interrupt-parent = <&intc>; 84 ranges; 85 86 usart3: serial@4000f000 { 87 compatible = "st,stm32h7-uart"; 88 reg = <0x4000f000 0x400>; 89 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 90 status = "disabled"; 91 }; 92 93 uart4: serial@40010000 { 94 compatible = "st,stm32h7-uart"; 95 reg = <0x40010000 0x400>; 96 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&rcc UART4_K>; 98 status = "disabled"; 99 }; 100 101 uart5: serial@40011000 { 102 compatible = "st,stm32h7-uart"; 103 reg = <0x40011000 0x400>; 104 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 105 status = "disabled"; 106 }; 107 108 uart7: serial@40018000 { 109 compatible = "st,stm32h7-uart"; 110 reg = <0x40018000 0x400>; 111 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 112 status = "disabled"; 113 }; 114 115 uart8: serial@40019000 { 116 compatible = "st,stm32h7-uart"; 117 reg = <0x40019000 0x400>; 118 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 119 status = "disabled"; 120 }; 121 122 usart6: serial@44003000 { 123 compatible = "st,stm32h7-uart"; 124 reg = <0x44003000 0x400>; 125 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 126 status = "disabled"; 127 }; 128 129 usart1: serial@4c000000 { 130 compatible = "st,stm32h7-uart"; 131 reg = <0x4c000000 0x400>; 132 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 133 status = "disabled"; 134 }; 135 136 usart2: serial@4c001000 { 137 compatible = "st,stm32h7-uart"; 138 reg = <0x4c001000 0x400>; 139 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 140 status = "disabled"; 141 }; 142 143 i2c3: i2c@4c004000 { 144 compatible = "st,stm32mp13-i2c"; 145 reg = <0x4c004000 0x400>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 st,syscfg-fmp = <&syscfg 0x4 0x4>; 149 i2c-analog-filter; 150 status = "disabled"; 151 }; 152 153 i2c4: i2c@4c005000 { 154 compatible = "st,stm32mp13-i2c"; 155 reg = <0x4c005000 0x400>; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 st,syscfg-fmp = <&syscfg 0x4 0x8>; 159 i2c-analog-filter; 160 status = "disabled"; 161 }; 162 163 i2c5: i2c@4c006000 { 164 compatible = "st,stm32mp13-i2c"; 165 reg = <0x4c006000 0x400>; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 st,syscfg-fmp = <&syscfg 0x4 0x10>; 169 i2c-analog-filter; 170 status = "disabled"; 171 }; 172 173 rcc: rcc@50000000 { 174 compatible = "st,stm32mp13-rcc", "syscon"; 175 reg = <0x50000000 0x1000>; 176 #address-cells = <1>; 177 #size-cells = <0>; 178 #clock-cells = <1>; 179 #reset-cells = <1>; 180 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, <&clk_lsi>, <&clk_csi>, <&clk_i2sin>; 181 clock-names = "clk-hse", "clk-hsi", "clk-lse", "clk-lsi", "clk-csi", "clk-i2sin"; 182 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 183 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 184 secure-interrupt-names = "wakeup"; 185 }; 186 187 syscfg: syscon@50020000 { 188 compatible = "st,stm32mp157-syscfg", "syscon"; 189 reg = <0x50020000 0x400>; 190 }; 191 192 bsec: efuse@5c005000 { 193 compatible = "st,stm32mp15-bsec"; 194 reg = <0x5c005000 0x400>; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 }; 198 199 tzc400: tzc@5c006000 { 200 compatible = "st,stm32mp1-tzc"; 201 reg = <0x5c006000 0x1000>; 202 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 203 st,mem-map = <0xc0000000 0x40000000>; 204 clocks = <&rcc TZC>; 205 }; 206 207 etzpc: etzpc@5c007000 { 208 compatible = "st,stm32-etzpc"; 209 reg = <0x5C007000 0x400>; 210 }; 211 212 stgen: stgen@5c008000 { 213 compatible = "st,stm32-stgen"; 214 reg = <0x5C008000 0x1000>; 215 }; 216 217 pinctrl: pin-controller@50002000 { 218 #address-cells = <1>; 219 #size-cells = <1>; 220 compatible = "st,stm32mp135-pinctrl"; 221 ranges = <0 0x50002000 0x8400>; 222 pins-are-numbered; 223 224 gpioa: gpio@50002000 { 225 gpio-controller; 226 #gpio-cells = <2>; 227 interrupt-controller; 228 #interrupt-cells = <2>; 229 clocks = <&rcc GPIOA>; 230 reg = <0x0 0x400>; 231 st,bank-name = "GPIOA"; 232 ngpios = <16>; 233 gpio-ranges = <&pinctrl 0 0 16>; 234 }; 235 236 gpiob: gpio@50003000 { 237 gpio-controller; 238 #gpio-cells = <2>; 239 interrupt-controller; 240 #interrupt-cells = <2>; 241 clocks = <&rcc GPIOB>; 242 reg = <0x1000 0x400>; 243 st,bank-name = "GPIOB"; 244 ngpios = <16>; 245 gpio-ranges = <&pinctrl 0 16 16>; 246 }; 247 248 gpioc: gpio@50004000 { 249 gpio-controller; 250 #gpio-cells = <2>; 251 interrupt-controller; 252 #interrupt-cells = <2>; 253 clocks = <&rcc GPIOC>; 254 reg = <0x2000 0x400>; 255 st,bank-name = "GPIOC"; 256 ngpios = <16>; 257 gpio-ranges = <&pinctrl 0 32 16>; 258 }; 259 260 gpiod: gpio@50005000 { 261 gpio-controller; 262 #gpio-cells = <2>; 263 interrupt-controller; 264 #interrupt-cells = <2>; 265 clocks = <&rcc GPIOD>; 266 reg = <0x3000 0x400>; 267 st,bank-name = "GPIOD"; 268 ngpios = <16>; 269 gpio-ranges = <&pinctrl 0 48 16>; 270 }; 271 272 gpioe: gpio@50006000 { 273 gpio-controller; 274 #gpio-cells = <2>; 275 interrupt-controller; 276 #interrupt-cells = <2>; 277 clocks = <&rcc GPIOE>; 278 reg = <0x4000 0x400>; 279 st,bank-name = "GPIOE"; 280 ngpios = <16>; 281 gpio-ranges = <&pinctrl 0 64 16>; 282 }; 283 284 gpiof: gpio@50007000 { 285 gpio-controller; 286 #gpio-cells = <2>; 287 interrupt-controller; 288 #interrupt-cells = <2>; 289 clocks = <&rcc GPIOF>; 290 reg = <0x5000 0x400>; 291 st,bank-name = "GPIOF"; 292 ngpios = <16>; 293 gpio-ranges = <&pinctrl 0 80 16>; 294 }; 295 296 gpiog: gpio@50008000 { 297 gpio-controller; 298 #gpio-cells = <2>; 299 interrupt-controller; 300 #interrupt-cells = <2>; 301 clocks = <&rcc GPIOG>; 302 reg = <0x6000 0x400>; 303 st,bank-name = "GPIOG"; 304 ngpios = <16>; 305 gpio-ranges = <&pinctrl 0 96 16>; 306 }; 307 308 gpioh: gpio@50009000 { 309 gpio-controller; 310 #gpio-cells = <2>; 311 interrupt-controller; 312 #interrupt-cells = <2>; 313 clocks = <&rcc GPIOH>; 314 reg = <0x7000 0x400>; 315 st,bank-name = "GPIOH"; 316 ngpios = <15>; 317 gpio-ranges = <&pinctrl 0 112 15>; 318 }; 319 320 gpioi: gpio@5000a000 { 321 gpio-controller; 322 #gpio-cells = <2>; 323 interrupt-controller; 324 #interrupt-cells = <2>; 325 clocks = <&rcc GPIOI>; 326 reg = <0x8000 0x400>; 327 st,bank-name = "GPIOI"; 328 ngpios = <8>; 329 gpio-ranges = <&pinctrl 0 128 8>; 330 }; 331 }; 332 }; 333}; 334