1// SPDX-License-Identifier: BSD-2-Clause 2/* 3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC 4 * 5 * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries 6 * 7 * Author: Eugen Hristev <eugen.hristev@microchip.com> 8 * Author: Claudiu Beznea <claudiu.beznea@microchip.com> 9 */ 10 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/dma/at91.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/interrupt-controller/irq.h> 17 18/ { 19 model = "Microchip SAMA7G5 family SoC"; 20 compatible = "microchip,sama7g5"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 interrupt-parent = <&gic>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a7"; 32 reg = <0x0>; 33 clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; 34 clock-names = "cpu"; 35 operating-points-v2 = <&cpu_opp_table>; 36 #cooling-cells = <2>; /* min followed by max */ 37 }; 38 }; 39 40 cpu_opp_table: opp-table { 41 compatible = "operating-points-v2"; 42 43 opp-90000000 { 44 opp-hz = /bits/ 64 <90000000>; 45 opp-microvolt = <1050000 1050000 1225000>; 46 clock-latency-ns = <320000>; 47 }; 48 49 opp-250000000 { 50 opp-hz = /bits/ 64 <250000000>; 51 opp-microvolt = <1050000 1050000 1225000>; 52 clock-latency-ns = <320000>; 53 }; 54 55 opp-600000000 { 56 opp-hz = /bits/ 64 <600000000>; 57 opp-microvolt = <1050000 1050000 1225000>; 58 clock-latency-ns = <320000>; 59 opp-suspend; 60 }; 61 62 opp-800000000 { 63 opp-hz = /bits/ 64 <800000000>; 64 opp-microvolt = <1150000 1125000 1225000>; 65 clock-latency-ns = <320000>; 66 }; 67 68 opp-1000000002 { 69 opp-hz = /bits/ 64 <1000000002>; 70 opp-microvolt = <1250000 1225000 1300000>; 71 clock-latency-ns = <320000>; 72 }; 73 }; 74 75 thermal-zones { 76 cpu_thermal: cpu-thermal { 77 polling-delay-passive = <1000>; 78 polling-delay = <5000>; 79 thermal-sensors = <&thermal_sensor>; 80 81 trips { 82 cpu_normal: cpu-alert0 { 83 temperature = <90000>; 84 hysteresis = <0>; 85 type = "passive"; 86 }; 87 88 cpu_hot: cpu-alert1 { 89 temperature = <95000>; 90 hysteresis = <0>; 91 type = "passive"; 92 }; 93 94 cpu_critical: cpu-critical { 95 temperature = <100000>; 96 hysteresis = <0>; 97 type = "critical"; 98 }; 99 }; 100 101 cooling-maps { 102 map0 { 103 trip = <&cpu_normal>; 104 }; 105 106 map1 { 107 trip = <&cpu_hot>; 108 }; 109 }; 110 }; 111 }; 112 113 clocks { 114 slow_xtal: slow_xtal { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 }; 118 119 main_xtal: main_xtal { 120 compatible = "fixed-clock"; 121 #clock-cells = <0>; 122 }; 123 124 usb_clk: usb_clk { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <48000000>; 128 }; 129 }; 130 131 utmi_clk: utmi-clk { 132 compatible = "microchip,sama7g5-utmi-clk"; 133 sfr-phandle = <&sfr>; 134 #clock-cells = <1>; 135 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; 136 clock-names = "utmi_clk"; 137 reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; 138 status = "disabled"; 139 }; 140 141 utmi { 142 compatible = "simple-bus"; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 146 usb_phy0: phy@0 { 147 compatible = "microchip,sama7g5-usb-phy"; 148 sfr-phandle = <&sfr>; 149 reg = <0>; 150 clock-names = "utmi_clk"; 151 status = "disabled"; 152 #phy-cells = <0>; 153 }; 154 155 usb_phy1: phy@1 { 156 compatible = "microchip,sama7g5-usb-phy"; 157 sfr-phandle = <&sfr>; 158 reg = <1>; 159 clock-names = "utmi_clk"; 160 status = "disabled"; 161 #phy-cells = <0>; 162 }; 163 164 usb_phy2: phy@2 { 165 compatible = "microchip,sama7g5-usb-phy"; 166 sfr-phandle = <&sfr>; 167 reg = <2>; 168 clock-names = "utmi_clk"; 169 status = "disabled"; 170 #phy-cells = <0>; 171 }; 172 }; 173 174 vddout25: fixed-regulator-vddout25 { 175 compatible = "regulator-fixed"; 176 177 regulator-name = "VDDOUT25"; 178 regulator-min-microvolt = <2500000>; 179 regulator-max-microvolt = <2500000>; 180 regulator-boot-on; 181 status = "disabled"; 182 }; 183 184 ns_sram: sram@100000 { 185 compatible = "atmel,sama5d2-sram", "mmio-sram"; 186 #address-cells = <1>; 187 #size-cells = <1>; 188 reg = <0x100000 0x3400>; 189 ranges; 190 status = "disabled"; 191 secure-status = "okay"; 192 }; 193 194 thermal_sensor: thermal-sensor { 195 compatible = "generic-adc-thermal"; 196 #thermal-sensor-cells = <0>; 197 io-channel-names = "sensor-channel"; 198 status = "disabled"; 199 }; 200 201 soc { 202 compatible = "simple-bus"; 203 #address-cells = <1>; 204 #size-cells = <1>; 205 ranges; 206 207 usb0: gadget@200000 { 208 #address-cells = <1>; 209 #size-cells = <0>; 210 compatible = "microchip,sama7g5-udc"; 211 reg = <0x00200000 0x100000 212 0xe0814000 0x400>; 213 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&pmc PMC_TYPE_PERIPHERAL 104>, <&usb_clk>; 215 clock-names = "pclk", "hclk"; 216 status = "disabled"; 217 }; 218 219 usb1: gadget@300000 { 220 #address-cells = <1>; 221 #size-cells = <0>; 222 compatible = "microchip,sama7g5-udc"; 223 reg = <0x00300000 0x100000 224 0xe0818000 0x400>; 225 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&pmc PMC_TYPE_PERIPHERAL 105>, <&usb_clk>; 227 clock-names = "pclk", "hclk"; 228 status = "disabled"; 229 }; 230 231 usb2: ohci@400000 { 232 compatible = "microchip,sama7g5-ohci", "usb-ohci"; 233 reg = <0x00400000 0x100000>; 234 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 235 clock-names = "ohci_clk", "hclk", "uhpck"; 236 status = "disabled"; 237 }; 238 239 usb3: ehci@500000 { 240 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 241 reg = <0x00500000 0x100000>; 242 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&usb_clk>, <&pmc PMC_TYPE_PERIPHERAL 106>; 244 clock-names = "usb_clk", "ehci_clk"; 245 status = "disabled"; 246 }; 247 248 nfc_sram: sram@600000 { 249 compatible = "mmio-sram"; 250 no-memory-wc; 251 reg = <0x00600000 0x2400>; 252 #address-cells = <1>; 253 #size-cells = <1>; 254 ranges = <0 0x00600000 0x2400>; 255 }; 256 257 nfc_io: nfc-io@10000000 { 258 compatible = "atmel,sama5d3-nfc-io", "syscon"; 259 reg = <0x10000000 0x8000000>; 260 }; 261 262 ebi: ebi@40000000 { 263 compatible = "atmel,sama5d3-ebi"; 264 #address-cells = <2>; 265 #size-cells = <1>; 266 atmel,smc = <&hsmc>; 267 reg = <0x40000000 0x20000000>; 268 ranges = <0x0 0x0 0x40000000 0x8000000 269 0x1 0x0 0x48000000 0x8000000 270 0x2 0x0 0x50000000 0x8000000 271 0x3 0x0 0x58000000 0x8000000>; 272 clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>; 273 status = "disabled"; 274 275 nand_controller: nand-controller { 276 compatible = "atmel,sama5d3-nand-controller"; 277 atmel,nfc-sram = <&nfc_sram>; 278 atmel,nfc-io = <&nfc_io>; 279 ecc-engine = <&pmecc>; 280 #address-cells = <2>; 281 #size-cells = <1>; 282 ranges; 283 status = "disabled"; 284 }; 285 }; 286 287 securam: sram@e0000000 { 288 compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; 289 reg = <0xe0000000 0x4000>; 290 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 ranges = <0 0xe0000000 0x4000>; 294 no-memory-wc; 295 status = "disabled"; 296 secure-status = "okay"; 297 }; 298 299 secumod: secumod@e0004000 { 300 compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; 301 reg = <0xe0004000 0x4000>; 302 gpio-controller; 303 #gpio-cells = <2>; 304 status = "disabled"; 305 secure-status = "okay"; 306 }; 307 308 sfrbu: sfr@e0008000 { 309 compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; 310 reg = <0xe0008000 0x20>; 311 }; 312 313 pioA: pinctrl@e0014000 { 314 compatible = "microchip,sama7g5-pinctrl"; 315 reg = <0xe0014000 0x800>; 316 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 321 interrupt-controller; 322 #interrupt-cells = <2>; 323 gpio-controller; 324 #gpio-cells = <2>; 325 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 326 status = "disabled"; 327 secure-status = "okay"; 328 }; 329 330 pmc: pmc@e0018000 { 331 compatible = "microchip,sama7g5-pmc", "syscon"; 332 reg = <0xe0018000 0x200>; 333 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 334 #clock-cells = <2>; 335 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 336 clock-names = "td_slck", "md_slck", "main_xtal"; 337 status = "disabled"; 338 secure-status = "okay"; 339 }; 340 341 reset_controller: reset-controller@e001d000 { 342 compatible = "microchip,sama7g5-rstc"; 343 reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; 344 #reset-cells = <1>; 345 clocks = <&clk32k 0>; 346 status = "disabled"; 347 secure-status = "okay"; 348 }; 349 350 shdwc: shdwc@e001d010 { 351 compatible = "microchip,sama7g5-shdwc", "syscon"; 352 reg = <0xe001d010 0x10>; 353 clocks = <&clk32k 0>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 atmel,wakeup-rtc-timer; 357 atmel,wakeup-rtt-timer; 358 status = "disabled"; 359 secure-status = "okay"; 360 }; 361 362 rtt: rtc@e001d020 { 363 compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; 364 reg = <0xe001d020 0x30>; 365 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&clk32k 0>; 367 }; 368 369 clk32k: clock-controller@e001d050 { 370 compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; 371 reg = <0xe001d050 0x4>; 372 clocks = <&slow_xtal>; 373 #clock-cells = <1>; 374 status = "disabled"; 375 secure-status = "okay"; 376 }; 377 378 gpbr: gpbr@e001d060 { 379 compatible = "microchip,sama7g5-gpbr", "syscon"; 380 reg = <0xe001d060 0x48>; 381 }; 382 383 rtc: rtc@e001d0a8 { 384 compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc"; 385 reg = <0xe001d0a8 0x30>; 386 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&clk32k 1>; 388 status = "disabled"; 389 secure-status = "okay"; 390 }; 391 392 ps_wdt: watchdog@e001d180 { 393 compatible = "microchip,sama7g5-wdt"; 394 reg = <0xe001d180 0x24>; 395 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&clk32k 0>; 397 status = "disabled"; 398 secure-status = "okay"; 399 }; 400 401 chipid@e0020000 { 402 compatible = "microchip,sama7g5-chipid"; 403 reg = <0xe0020000 0x8>; 404 }; 405 406 tcb1: timer@e0800000 { 407 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 reg = <0xe0800000 0x100>; 411 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>; 413 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 414 status = "disabled"; 415 secure-status = "okay"; 416 }; 417 418 hsmc: hsmc@e0808000 { 419 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 420 reg = <0xe0808000 0x1000>; 421 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 423 #address-cells = <1>; 424 #size-cells = <1>; 425 ranges; 426 427 pmecc: ecc-engine@e0808070 { 428 compatible = "atmel,sama5d2-pmecc"; 429 reg = <0xe0808070 0x490>, 430 <0xe0808500 0x200>; 431 }; 432 }; 433 434 qspi0: spi@e080c000 { 435 compatible = "microchip,sama7g5-ospi"; 436 reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; 437 reg-names = "qspi_base", "qspi_mmap"; 438 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 439 dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, 440 <&dma0 AT91_XDMAC_DT_PERID(40)>; 441 dma-names = "tx", "rx"; 442 clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; 443 clock-names = "pclk", "gclk"; 444 assigned-clocks = <&pmc PMC_TYPE_GCK 78>; 445 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 446 assigned-clock-rates = <133000000>; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 status = "disabled"; 450 }; 451 452 qspi1: spi@e0810000 { 453 compatible = "microchip,sama7g5-qspi"; 454 reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; 455 reg-names = "qspi_base", "qspi_mmap"; 456 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 457 dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, 458 <&dma0 AT91_XDMAC_DT_PERID(42)>; 459 dma-names = "tx", "rx"; 460 clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; 461 clock-names = "pclk", "gclk"; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 status = "disabled"; 465 }; 466 467 can0: can@e0828000 { 468 compatible = "bosch,m_can"; 469 reg = <0xe0828000 0x100>, <0x100000 0x7800>; 470 reg-names = "m_can", "message_ram"; 471 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 472 GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 473 interrupt-names = "int0", "int1"; 474 clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; 475 clock-names = "hclk", "cclk"; 476 assigned-clocks = <&pmc PMC_TYPE_GCK 61>; 477 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 478 assigned-clock-rates = <40000000>; 479 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; 480 status = "disabled"; 481 }; 482 483 can1: can@e082c000 { 484 compatible = "bosch,m_can"; 485 reg = <0xe082c000 0x100>, <0x100000 0xbc00>; 486 reg-names = "m_can", "message_ram"; 487 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 488 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 489 interrupt-names = "int0", "int1"; 490 clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; 491 clock-names = "hclk", "cclk"; 492 assigned-clocks = <&pmc PMC_TYPE_GCK 62>; 493 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 494 assigned-clock-rates = <40000000>; 495 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; 496 status = "disabled"; 497 }; 498 499 can2: can@e0830000 { 500 compatible = "bosch,m_can"; 501 reg = <0xe0830000 0x100>, <0x100000 0x10000>; 502 reg-names = "m_can", "message_ram"; 503 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 504 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 505 interrupt-names = "int0", "int1"; 506 clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; 507 clock-names = "hclk", "cclk"; 508 assigned-clocks = <&pmc PMC_TYPE_GCK 63>; 509 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 510 assigned-clock-rates = <40000000>; 511 bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; 512 status = "disabled"; 513 }; 514 515 can3: can@e0834000 { 516 compatible = "bosch,m_can"; 517 reg = <0xe0834000 0x100>, <0x110000 0x4400>; 518 reg-names = "m_can", "message_ram"; 519 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 520 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 521 interrupt-names = "int0", "int1"; 522 clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; 523 clock-names = "hclk", "cclk"; 524 assigned-clocks = <&pmc PMC_TYPE_GCK 64>; 525 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 526 assigned-clock-rates = <40000000>; 527 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 528 status = "disabled"; 529 }; 530 531 can4: can@e0838000 { 532 compatible = "bosch,m_can"; 533 reg = <0xe0838000 0x100>, <0x110000 0x8800>; 534 reg-names = "m_can", "message_ram"; 535 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 536 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 537 interrupt-names = "int0", "int1"; 538 clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; 539 clock-names = "hclk", "cclk"; 540 assigned-clocks = <&pmc PMC_TYPE_GCK 65>; 541 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 542 assigned-clock-rates = <40000000>; 543 bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; 544 status = "disabled"; 545 }; 546 547 can5: can@e083c000 { 548 compatible = "bosch,m_can"; 549 reg = <0xe083c000 0x100>, <0x110000 0xcc00>; 550 reg-names = "m_can", "message_ram"; 551 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 552 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 553 interrupt-names = "int0", "int1"; 554 clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; 555 clock-names = "hclk", "cclk"; 556 assigned-clocks = <&pmc PMC_TYPE_GCK 66>; 557 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 558 assigned-clock-rates = <40000000>; 559 bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>; 560 status = "disabled"; 561 }; 562 563 adc: adc@e1000000 { 564 compatible = "microchip,sama7g5-adc"; 565 reg = <0xe1000000 0x200>; 566 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&pmc PMC_TYPE_GCK 26>; 568 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 569 assigned-clock-rates = <100000000>; 570 clock-names = "adc_clk"; 571 dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>; 572 dma-names = "rx"; 573 atmel,min-sample-rate-hz = <200000>; 574 atmel,max-sample-rate-hz = <20000000>; 575 atmel,startup-time-ms = <4>; 576 #io-channel-cells = <1>; 577 nvmem-cells = <&temperature_calib>; 578 nvmem-cell-names = "temperature_calib"; 579 status = "disabled"; 580 }; 581 582 sdmmc0: mmc@e1204000 { 583 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 584 reg = <0xe1204000 0x4000>; 585 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; 587 clock-names = "hclock", "multclk"; 588 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 589 assigned-clocks = <&pmc PMC_TYPE_GCK 80>; 590 assigned-clock-rates = <200000000>; 591 microchip,sdcal-inverted; 592 status = "disabled"; 593 }; 594 595 sdmmc1: mmc@e1208000 { 596 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 597 reg = <0xe1208000 0x4000>; 598 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; 600 clock-names = "hclock", "multclk"; 601 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 602 assigned-clocks = <&pmc PMC_TYPE_GCK 81>; 603 assigned-clock-rates = <200000000>; 604 microchip,sdcal-inverted; 605 status = "disabled"; 606 }; 607 608 sdmmc2: mmc@e120c000 { 609 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 610 reg = <0xe120c000 0x4000>; 611 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; 613 clock-names = "hclock", "multclk"; 614 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 615 assigned-clocks = <&pmc PMC_TYPE_GCK 82>; 616 assigned-clock-rates = <200000000>; 617 microchip,sdcal-inverted; 618 status = "disabled"; 619 }; 620 621 csi2host: csi2host@e1400000 { 622 compatible = "snps,dw-csi"; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 reg = <0xe1400000 0x7FF>; 626 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>, <&pmc PMC_TYPE_GCK 33>; 628 clock-names = "perclk", "phyclk"; 629 assigned-clocks = <&pmc PMC_TYPE_GCK 33>; 630 assigned-clock-rates = <26600000>; 631 snps,output-type = <1>; 632 phys = <&csi_dphy>; 633 status = "disabled"; 634 635 port@1 { 636 reg = <1>; 637 csi2host_in: endpoint { 638 }; 639 }; 640 641 port@2 { 642 reg = <2>; 643 csi2host_out: endpoint { 644 }; 645 }; 646 }; 647 648 csi_dphy: dphy@e1400040 { 649 compatible = "snps,dw-dphy-rx"; 650 #phy-cells = <0>; 651 bus-width = <8>; 652 snps,dphy-frequency = <900000>; 653 snps,phy_type = <0>; 654 reg = <0xe1400040 0x20>; 655 status = "disabled"; 656 }; 657 658 csi2dc: csi2dc@e1404000 { 659 compatible = "microchip,sama7g5-csi2dc"; 660 reg = <0xe1404000 0x500>; 661 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; 662 clock-names = "pclk", "scck"; 663 assigned-clocks = <&xisc>; 664 assigned-clock-rates = <266000000>; 665 status = "disabled"; 666 667 ports { 668 #address-cells = <1>; 669 #size-cells = <0>; 670 port@0 { 671 reg = <0>; 672 csi2dc_in: endpoint { 673 }; 674 }; 675 676 port@1 { 677 reg = <1>; 678 csi2dc_out: endpoint { 679 bus-width = <14>; 680 hsync-active = <1>; 681 vsync-active = <1>; 682 remote-endpoint = <&xisc_in>; 683 }; 684 }; 685 }; 686 }; 687 688 xisc: xisc@e1408000 { 689 compatible = "microchip,sama7g5-isc"; 690 reg = <0xe1408000 0x2000>; 691 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; 693 clock-names = "hclock"; 694 #clock-cells = <0>; 695 clock-output-names = "isc-mck"; 696 status = "disabled"; 697 698 port { 699 xisc_in: endpoint { 700 bus-type = <5>; /* Parallel */ 701 bus-width = <14>; 702 hsync-active = <1>; 703 vsync-active = <1>; 704 remote-endpoint = <&csi2dc_out>; 705 }; 706 }; 707 }; 708 709 pwm: pwm@e1604000 { 710 compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; 711 reg = <0xe1604000 0x4000>; 712 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 713 #pwm-cells = <3>; 714 clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; 715 status = "disabled"; 716 }; 717 718 pdmc0: sound@e1608000 { 719 compatible = "microchip,sama7g5-pdmc"; 720 reg = <0xe1608000 0x1000>; 721 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 722 #sound-dai-cells = <0>; 723 dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>; 724 dma-names = "rx"; 725 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>; 726 clock-names = "pclk", "gclk"; 727 sound-name-prefix = "PDMC0"; 728 status = "disabled"; 729 }; 730 731 pdmc1: sound@e160c000 { 732 compatible = "microchip,sama7g5-pdmc"; 733 reg = <0xe160c000 0x1000>; 734 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 735 #sound-dai-cells = <0>; 736 dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>; 737 dma-names = "rx"; 738 clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>; 739 clock-names = "pclk", "gclk"; 740 sound-name-prefix = "PDMC1"; 741 status = "disabled"; 742 }; 743 744 asrc: sound@e1610000 { 745 compatible = "microchip,sama7g5-asrc"; 746 reg = <0xe1610000 0x1000>; 747 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 748 #sound-dai-cells = <1>; 749 dmas = <&dma0 AT91_XDMAC_DT_PERID(55)>, 750 <&dma0 AT91_XDMAC_DT_PERID(56)>, 751 <&dma0 AT91_XDMAC_DT_PERID(57)>, 752 <&dma0 AT91_XDMAC_DT_PERID(58)>, 753 <&dma0 AT91_XDMAC_DT_PERID(59)>, 754 <&dma0 AT91_XDMAC_DT_PERID(60)>, 755 <&dma0 AT91_XDMAC_DT_PERID(61)>, 756 <&dma0 AT91_XDMAC_DT_PERID(62)>; 757 dma-names = "rx0", "tx0", "rx1", "tx1", 758 "rx2", "tx2", "rx3", "tx3"; 759 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; 760 clock-names = "pclk", "gclk"; 761 microchip,triggers = <&i2s0>, <&i2s1>, <&pdmc0>, <&pdmc1>, 762 <&ssc0>, <&ssc1>, <&spdiftx>, <&spdifrx>; 763 microchip,trigger-indexes = <1>, <2>, <3>, <4>, <5>, <8>, <9>, <10>; 764 assigned-clocks = <&pmc PMC_TYPE_GCK 30>; 765 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_AUDIOPMCPLL>; 766 status = "disabled"; 767 }; 768 769 spdifrx: spdifrx@e1614000 { 770 #sound-dai-cells = <0>; 771 compatible = "microchip,sama7g5-spdifrx"; 772 reg = <0xe1614000 0x4000>; 773 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 774 dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; 775 dma-names = "rx"; 776 clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; 777 clock-names = "pclk", "gclk"; 778 status = "disabled"; 779 sound-name-prefix = "SPDIFRX0"; 780 }; 781 782 spdiftx: spdiftx@e1618000 { 783 #sound-dai-cells = <0>; 784 compatible = "microchip,sama7g5-spdiftx"; 785 reg = <0xe1618000 0x4000>; 786 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 787 dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; 788 dma-names = "tx"; 789 clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; 790 clock-names = "pclk", "gclk"; 791 sound-name-prefix = "SPDIFTX0"; 792 }; 793 794 i2s0: i2s@e161c000 { 795 compatible = "microchip,sama7g5-i2smcc"; 796 #sound-dai-cells = <0>; 797 reg = <0xe161c000 0x4000>; 798 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 799 dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; 800 dma-names = "tx", "rx"; 801 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 802 clock-names = "pclk", "gclk"; 803 sound-name-prefix = "I2SMCC0"; 804 status = "disabled"; 805 }; 806 807 i2s1: i2s@e1620000 { 808 compatible = "microchip,sama7g5-i2smcc"; 809 #sound-dai-cells = <0>; 810 reg = <0xe1620000 0x4000>; 811 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 812 dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; 813 dma-names = "tx", "rx"; 814 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 815 clock-names = "pclk", "gclk"; 816 sound-name-prefix = "I2SMCC1"; 817 status = "disabled"; 818 }; 819 820 sfr: sfr@e1624000 { 821 compatible = "microchip,sama7g5-sfr", "syscon"; 822 reg = <0xe1624000 0x4000>; 823 }; 824 825 eic: interrupt-controller@e1628000 { 826 compatible = "microchip,sama7g5-eic"; 827 reg = <0xe1628000 0xec>; 828 interrupt-parent = <&gic>; 829 interrupt-controller; 830 #interrupt-cells = <2>; 831 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 834 clock-names = "pclk"; 835 status = "disabled"; 836 }; 837 838 pit64b0: timer@e1800000 { 839 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 840 reg = <0xe1800000 0x4000>; 841 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; 843 clock-names = "pclk", "gclk"; 844 }; 845 846 pit64b1: timer@e1804000 { 847 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 848 reg = <0xe1804000 0x4000>; 849 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; 851 clock-names = "pclk", "gclk"; 852 }; 853 854 ssc0: sound@e180c000 { 855 compatible = "atmel,at91sam9g45-ssc"; 856 reg = <0xe180c000 0x1000>; 857 #sound-dai-cells = <0>; 858 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 859 dmas = <&dma0 AT91_XDMAC_DT_PERID(44)>, 860 <&dma0 AT91_XDMAC_DT_PERID(45)>; 861 dma-names = "rx", "tx"; 862 clocks = <&pmc PMC_TYPE_PERIPHERAL 86>; 863 clock-names = "pclk"; 864 sound-name-prefix = "SSC0"; 865 status = "disabled"; 866 }; 867 868 aes: crypto@e1810000 { 869 compatible = "atmel,at91sam9g46-aes"; 870 reg = <0xe1810000 0x100>; 871 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 873 clock-names = "aes_clk"; 874 dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, 875 <&dma0 AT91_XDMAC_DT_PERID(2)>; 876 dma-names = "tx", "rx"; 877 status = "okay"; 878 }; 879 880 sha: crypto@e1814000 { 881 compatible = "atmel,at91sam9g46-sha"; 882 reg = <0xe1814000 0x100>; 883 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 884 clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; 885 clock-names = "sha_clk"; 886 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; 887 dma-names = "tx"; 888 status = "okay"; 889 }; 890 891 flx0: flexcom@e1818000 { 892 compatible = "atmel,sama5d2-flexcom"; 893 reg = <0xe1818000 0x200>; 894 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 895 #address-cells = <1>; 896 #size-cells = <1>; 897 ranges = <0x0 0xe1818000 0x800>; 898 status = "disabled"; 899 900 uart0: serial@200 { 901 compatible = "atmel,at91sam9260-usart"; 902 reg = <0x200 0x200>; 903 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 905 clock-names = "usart"; 906 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, 907 <&dma1 AT91_XDMAC_DT_PERID(5)>; 908 dma-names = "tx", "rx"; 909 atmel,use-dma-rx; 910 atmel,use-dma-tx; 911 status = "disabled"; 912 }; 913 }; 914 915 flx1: flexcom@e181c000 { 916 compatible = "atmel,sama5d2-flexcom"; 917 reg = <0xe181c000 0x200>; 918 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 919 #address-cells = <1>; 920 #size-cells = <1>; 921 ranges = <0x0 0xe181c000 0x800>; 922 status = "disabled"; 923 924 i2c1: i2c@600 { 925 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 926 reg = <0x600 0x200>; 927 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 931 atmel,fifo-size = <32>; 932 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 933 <&dma0 AT91_XDMAC_DT_PERID(7)>; 934 dma-names = "tx", "rx"; 935 status = "disabled"; 936 }; 937 }; 938 939 flx3: flexcom@e1824000 { 940 compatible = "atmel,sama5d2-flexcom"; 941 reg = <0xe1824000 0x200>; 942 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 943 #address-cells = <1>; 944 #size-cells = <1>; 945 ranges = <0x0 0xe1824000 0x800>; 946 status = "disabled"; 947 948 uart3: serial@200 { 949 compatible = "atmel,at91sam9260-usart"; 950 reg = <0x200 0x200>; 951 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 953 clock-names = "usart"; 954 dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, 955 <&dma1 AT91_XDMAC_DT_PERID(11)>; 956 dma-names = "tx", "rx"; 957 atmel,use-dma-rx; 958 atmel,use-dma-tx; 959 status = "disabled"; 960 }; 961 }; 962 963 ssc1: sound@e200c000 { 964 compatible = "atmel,at91sam9g45-ssc"; 965 reg = <0xe200c000 0x1000>; 966 #sound-dai-cells = <0>; 967 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 968 dmas = <&dma0 AT91_XDMAC_DT_PERID(46)>, 969 <&dma0 AT91_XDMAC_DT_PERID(47)>; 970 dma-names = "rx", "tx"; 971 clocks = <&pmc PMC_TYPE_PERIPHERAL 87>; 972 clock-names = "pclk"; 973 sound-name-prefix = "SSC1"; 974 status = "disabled"; 975 }; 976 977 trng: rng@e2010000 { 978 compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; 979 reg = <0xe2010000 0x100>; 980 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; 982 status = "disabled"; 983 secure-status = "okay"; 984 }; 985 986 tdes: crypto@e2014000 { 987 compatible = "atmel,at91sam9g46-tdes"; 988 reg = <0xe2014000 0x100>; 989 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; 991 clock-names = "tdes_clk"; 992 dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, 993 <&dma0 AT91_XDMAC_DT_PERID(53)>; 994 dma-names = "tx", "rx"; 995 status = "okay"; 996 }; 997 998 flx4: flexcom@e2018000 { 999 compatible = "atmel,sama5d2-flexcom"; 1000 reg = <0xe2018000 0x200>; 1001 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 1002 #address-cells = <1>; 1003 #size-cells = <1>; 1004 ranges = <0x0 0xe2018000 0x800>; 1005 status = "disabled"; 1006 1007 uart4: serial@200 { 1008 compatible = "atmel,at91sam9260-usart"; 1009 reg = <0x200 0x200>; 1010 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 1012 clock-names = "usart"; 1013 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, 1014 <&dma1 AT91_XDMAC_DT_PERID(13)>; 1015 dma-names = "tx", "rx"; 1016 atmel,use-dma-rx; 1017 atmel,use-dma-tx; 1018 atmel,fifo-size = <16>; 1019 status = "disabled"; 1020 }; 1021 }; 1022 1023 flx7: flexcom@e2024000 { 1024 compatible = "atmel,sama5d2-flexcom"; 1025 reg = <0xe2024000 0x200>; 1026 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 1027 #address-cells = <1>; 1028 #size-cells = <1>; 1029 ranges = <0x0 0xe2024000 0x800>; 1030 status = "disabled"; 1031 1032 uart7: serial@200 { 1033 compatible = "atmel,at91sam9260-usart"; 1034 reg = <0x200 0x200>; 1035 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1036 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 1037 clock-names = "usart"; 1038 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 1039 <&dma1 AT91_XDMAC_DT_PERID(19)>; 1040 dma-names = "tx", "rx"; 1041 atmel,use-dma-rx; 1042 atmel,use-dma-tx; 1043 atmel,fifo-size = <16>; 1044 status = "disabled"; 1045 }; 1046 }; 1047 1048 gmac0: ethernet@e2800000 { 1049 compatible = "microchip,sama7g5-gem"; 1050 reg = <0xe2800000 0x1000>; 1051 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 1052 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 1053 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 1054 GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 1055 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 1056 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1057 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; 1058 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 1059 assigned-clocks = <&pmc PMC_TYPE_GCK 51>; 1060 assigned-clock-rates = <125000000>; 1061 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_ETHPLL>; 1062 status = "disabled"; 1063 }; 1064 1065 gmac1: ethernet@e2804000 { 1066 compatible = "microchip,sama7g5-emac"; 1067 reg = <0xe2804000 0x1000>; 1068 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 1069 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_GCK 54>; 1071 clock-names = "pclk", "hclk", "tsu_clk"; 1072 assigned-clocks = <&pmc PMC_TYPE_GCK 54>; 1073 assigned-clock-rates = <200000000>; 1074 status = "disabled"; 1075 }; 1076 1077 dma0: dma-controller@e2808000 { 1078 compatible = "microchip,sama7g5-dma"; 1079 reg = <0xe2808000 0x1000>; 1080 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1081 #dma-cells = <1>; 1082 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 1083 clock-names = "dma_clk"; 1084 status = "disabled"; 1085 }; 1086 1087 dma1: dma-controller@e280c000 { 1088 compatible = "microchip,sama7g5-dma"; 1089 reg = <0xe280c000 0x1000>; 1090 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1091 #dma-cells = <1>; 1092 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 1093 clock-names = "dma_clk"; 1094 status = "disabled"; 1095 }; 1096 1097 /* Place dma2 here despite it's address */ 1098 dma2: dma-controller@e1200000 { 1099 compatible = "microchip,sama7g5-dma"; 1100 reg = <0xe1200000 0x1000>; 1101 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1102 #dma-cells = <1>; 1103 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 1104 clock-names = "dma_clk"; 1105 dma-requests = <0>; 1106 status = "disabled"; 1107 }; 1108 1109 tcb0: timer@e2814000 { 1110 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 reg = <0xe2814000 0x100>; 1114 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1115 clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>; 1116 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 1117 }; 1118 1119 flx8: flexcom@e2818000 { 1120 compatible = "atmel,sama5d2-flexcom"; 1121 reg = <0xe2818000 0x200>; 1122 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 1123 #address-cells = <1>; 1124 #size-cells = <1>; 1125 ranges = <0x0 0xe2818000 0x800>; 1126 status = "disabled"; 1127 1128 i2c8: i2c@600 { 1129 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 1130 reg = <0x600 0x200>; 1131 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 1135 atmel,fifo-size = <32>; 1136 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 1137 <&dma0 AT91_XDMAC_DT_PERID(21)>; 1138 dma-names = "tx", "rx"; 1139 status = "disabled"; 1140 }; 1141 }; 1142 1143 flx9: flexcom@e281c000 { 1144 compatible = "atmel,sama5d2-flexcom"; 1145 reg = <0xe281c000 0x200>; 1146 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1147 #address-cells = <1>; 1148 #size-cells = <1>; 1149 ranges = <0x0 0xe281c000 0x800>; 1150 status = "disabled"; 1151 1152 i2c9: i2c@600 { 1153 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 1154 reg = <0x600 0x200>; 1155 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1159 atmel,fifo-size = <32>; 1160 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 1161 <&dma0 AT91_XDMAC_DT_PERID(23)>; 1162 dma-names = "tx", "rx"; 1163 status = "disabled"; 1164 }; 1165 }; 1166 1167 flx11: flexcom@e2824000 { 1168 compatible = "atmel,sama5d2-flexcom"; 1169 reg = <0xe2824000 0x200>; 1170 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 1171 #address-cells = <1>; 1172 #size-cells = <1>; 1173 ranges = <0x0 0xe2824000 0x800>; 1174 status = "disabled"; 1175 1176 spi11: spi@400 { 1177 compatible = "atmel,at91rm9200-spi"; 1178 reg = <0x400 0x200>; 1179 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1180 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 1181 clock-names = "spi_clk"; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 atmel,fifo-size = <32>; 1185 dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, 1186 <&dma0 AT91_XDMAC_DT_PERID(27)>; 1187 dma-names = "tx", "rx"; 1188 status = "disabled"; 1189 }; 1190 }; 1191 1192 uddrc: uddrc@e3800000 { 1193 compatible = "microchip,sama7g5-uddrc"; 1194 reg = <0xe3800000 0x4000>; 1195 }; 1196 1197 ddr3phy: ddr3phy@e3804000 { 1198 compatible = "microchip,sama7g5-ddr3phy"; 1199 reg = <0xe3804000 0x1000>; 1200 }; 1201 1202 otpc: efuse@e8c00000 { 1203 compatible = "microchip,sama7g5-otpc", "syscon"; 1204 reg = <0xe8c00000 0x100>; 1205 #address-cells = <1>; 1206 #size-cells = <1>; 1207 1208 temperature_calib: calib@1 { 1209 status = "disabled"; 1210 }; 1211 }; 1212 1213 gic: interrupt-controller@e8c11000 { 1214 compatible = "arm,cortex-a7-gic"; 1215 #interrupt-cells = <3>; 1216 #address-cells = <0>; 1217 interrupt-controller; 1218 reg = <0xe8c11000 0x1000>, 1219 <0xe8c12000 0x2000>; 1220 }; 1221 }; 1222}; 1223