1// SPDX-License-Identifier: BSD-2-Clause 2/* 3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC 4 * 5 * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries 6 * 7 * Author: Eugen Hristev <eugen.hristev@microchip.com> 8 * Author: Claudiu Beznea <claudiu.beznea@microchip.com> 9 */ 10 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/dma/at91.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/interrupt-controller/irq.h> 17 18/ { 19 model = "Microchip SAMA7G5 family SoC"; 20 compatible = "microchip,sama7g5"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 interrupt-parent = <&gic>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a7"; 32 reg = <0x0>; 33 clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; 34 clock-names = "cpu"; 35 operating-points-v2 = <&cpu_opp_table>; 36 #cooling-cells = <2>; /* min followed by max */ 37 }; 38 }; 39 40 cpu_opp_table: opp-table { 41 compatible = "operating-points-v2"; 42 43 opp-90000000 { 44 opp-hz = /bits/ 64 <90000000>; 45 opp-microvolt = <1050000 1050000 1225000>; 46 clock-latency-ns = <320000>; 47 }; 48 49 opp-250000000 { 50 opp-hz = /bits/ 64 <250000000>; 51 opp-microvolt = <1050000 1050000 1225000>; 52 clock-latency-ns = <320000>; 53 }; 54 55 opp-600000000 { 56 opp-hz = /bits/ 64 <600000000>; 57 opp-microvolt = <1050000 1050000 1225000>; 58 clock-latency-ns = <320000>; 59 opp-suspend; 60 }; 61 62 opp-800000000 { 63 opp-hz = /bits/ 64 <800000000>; 64 opp-microvolt = <1150000 1125000 1225000>; 65 clock-latency-ns = <320000>; 66 }; 67 68 opp-1000000002 { 69 opp-hz = /bits/ 64 <1000000002>; 70 opp-microvolt = <1250000 1225000 1300000>; 71 clock-latency-ns = <320000>; 72 }; 73 }; 74 75 thermal-zones { 76 cpu_thermal: cpu-thermal { 77 polling-delay-passive = <1000>; 78 polling-delay = <5000>; 79 thermal-sensors = <&thermal_sensor>; 80 81 trips { 82 cpu_normal: cpu-alert0 { 83 temperature = <90000>; 84 hysteresis = <0>; 85 type = "passive"; 86 }; 87 88 cpu_hot: cpu-alert1 { 89 temperature = <95000>; 90 hysteresis = <0>; 91 type = "passive"; 92 }; 93 94 cpu_critical: cpu-critical { 95 temperature = <100000>; 96 hysteresis = <0>; 97 type = "critical"; 98 }; 99 }; 100 101 cooling-maps { 102 map0 { 103 trip = <&cpu_normal>; 104 }; 105 106 map1 { 107 trip = <&cpu_hot>; 108 }; 109 }; 110 }; 111 }; 112 113 clocks { 114 slow_xtal: slow_xtal { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 }; 118 119 main_xtal: main_xtal { 120 compatible = "fixed-clock"; 121 #clock-cells = <0>; 122 }; 123 124 usb_clk: usb_clk { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <48000000>; 128 }; 129 }; 130 131 utmi_clk: utmi-clk { 132 compatible = "microchip,sama7g5-utmi-clk"; 133 sfr-phandle = <&sfr>; 134 #clock-cells = <1>; 135 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; 136 clock-names = "utmi_clk"; 137 reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; 138 status = "disabled"; 139 }; 140 141 utmi { 142 compatible = "simple-bus"; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 146 usb_phy0: phy@0 { 147 compatible = "microchip,sama7g5-usb-phy"; 148 sfr-phandle = <&sfr>; 149 reg = <0>; 150 clock-names = "utmi_clk"; 151 status = "disabled"; 152 #phy-cells = <0>; 153 }; 154 155 usb_phy1: phy@1 { 156 compatible = "microchip,sama7g5-usb-phy"; 157 sfr-phandle = <&sfr>; 158 reg = <1>; 159 clock-names = "utmi_clk"; 160 status = "disabled"; 161 #phy-cells = <0>; 162 }; 163 164 usb_phy2: phy@2 { 165 compatible = "microchip,sama7g5-usb-phy"; 166 sfr-phandle = <&sfr>; 167 reg = <2>; 168 clock-names = "utmi_clk"; 169 status = "disabled"; 170 #phy-cells = <0>; 171 }; 172 }; 173 174 vddout25: fixed-regulator-vddout25 { 175 compatible = "regulator-fixed"; 176 177 regulator-name = "VDDOUT25"; 178 regulator-min-microvolt = <2500000>; 179 regulator-max-microvolt = <2500000>; 180 regulator-boot-on; 181 status = "disabled"; 182 }; 183 184 ns_sram: sram@100000 { 185 compatible = "atmel,sama5d2-sram", "mmio-sram"; 186 #address-cells = <1>; 187 #size-cells = <1>; 188 reg = <0x100000 0x3400>; 189 ranges; 190 status = "disabled"; 191 secure-status = "okay"; 192 }; 193 194 thermal_sensor: thermal-sensor { 195 compatible = "generic-adc-thermal"; 196 #thermal-sensor-cells = <0>; 197 io-channel-names = "sensor-channel"; 198 status = "disabled"; 199 }; 200 201 soc { 202 compatible = "simple-bus"; 203 #address-cells = <1>; 204 #size-cells = <1>; 205 ranges; 206 207 usb0: gadget@200000 { 208 #address-cells = <1>; 209 #size-cells = <0>; 210 compatible = "microchip,sama7g5-udc"; 211 reg = <0x00200000 0x100000 212 0xe0814000 0x400>; 213 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&pmc PMC_TYPE_PERIPHERAL 104>, <&usb_clk>; 215 clock-names = "pclk", "hclk"; 216 status = "disabled"; 217 }; 218 219 usb1: gadget@300000 { 220 #address-cells = <1>; 221 #size-cells = <0>; 222 compatible = "microchip,sama7g5-udc"; 223 reg = <0x00300000 0x100000 224 0xe0818000 0x400>; 225 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&pmc PMC_TYPE_PERIPHERAL 105>, <&usb_clk>; 227 clock-names = "pclk", "hclk"; 228 status = "disabled"; 229 }; 230 231 usb2: ohci@400000 { 232 compatible = "microchip,sama7g5-ohci", "usb-ohci"; 233 reg = <0x00400000 0x100000>; 234 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 235 clock-names = "ohci_clk", "hclk", "uhpck"; 236 status = "disabled"; 237 }; 238 239 usb3: ehci@500000 { 240 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 241 reg = <0x00500000 0x100000>; 242 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&usb_clk>, <&pmc PMC_TYPE_PERIPHERAL 106>; 244 clock-names = "usb_clk", "ehci_clk"; 245 status = "disabled"; 246 }; 247 248 nfc_sram: sram@600000 { 249 compatible = "mmio-sram"; 250 no-memory-wc; 251 reg = <0x00600000 0x2400>; 252 #address-cells = <1>; 253 #size-cells = <1>; 254 ranges = <0 0x00600000 0x2400>; 255 }; 256 257 nfc_io: nfc-io@10000000 { 258 compatible = "atmel,sama5d3-nfc-io", "syscon"; 259 reg = <0x10000000 0x8000000>; 260 }; 261 262 ebi: ebi@40000000 { 263 compatible = "atmel,sama5d3-ebi"; 264 #address-cells = <2>; 265 #size-cells = <1>; 266 atmel,smc = <&hsmc>; 267 reg = <0x40000000 0x20000000>; 268 ranges = <0x0 0x0 0x40000000 0x8000000 269 0x1 0x0 0x48000000 0x8000000 270 0x2 0x0 0x50000000 0x8000000 271 0x3 0x0 0x58000000 0x8000000>; 272 clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>; 273 status = "disabled"; 274 275 nand_controller: nand-controller { 276 compatible = "atmel,sama5d3-nand-controller"; 277 atmel,nfc-sram = <&nfc_sram>; 278 atmel,nfc-io = <&nfc_io>; 279 ecc-engine = <&pmecc>; 280 #address-cells = <2>; 281 #size-cells = <1>; 282 ranges; 283 status = "disabled"; 284 }; 285 }; 286 287 securam: sram@e0000000 { 288 compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; 289 reg = <0xe0000000 0x4000>; 290 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 ranges = <0 0xe0000000 0x4000>; 294 no-memory-wc; 295 status = "disabled"; 296 secure-status = "okay"; 297 }; 298 299 secumod: secumod@e0004000 { 300 compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; 301 reg = <0xe0004000 0x4000>; 302 gpio-controller; 303 #gpio-cells = <2>; 304 status = "disabled"; 305 secure-status = "okay"; 306 }; 307 308 sfrbu: sfr@e0008000 { 309 compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; 310 reg = <0xe0008000 0x20>; 311 }; 312 313 pioA: pinctrl@e0014000 { 314 compatible = "microchip,sama7g5-pinctrl"; 315 reg = <0xe0014000 0x800>; 316 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 321 interrupt-controller; 322 #interrupt-cells = <2>; 323 gpio-controller; 324 #gpio-cells = <2>; 325 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 326 status = "disabled"; 327 secure-status = "okay"; 328 }; 329 330 pmc: pmc@e0018000 { 331 compatible = "microchip,sama7g5-pmc", "syscon"; 332 reg = <0xe0018000 0x200>; 333 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 334 #clock-cells = <2>; 335 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 336 clock-names = "td_slck", "md_slck", "main_xtal"; 337 status = "disabled"; 338 secure-status = "okay"; 339 }; 340 341 reset_controller: reset-controller@e001d000 { 342 compatible = "microchip,sama7g5-rstc"; 343 reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; 344 #reset-cells = <1>; 345 clocks = <&clk32k 0>; 346 status = "disabled"; 347 secure-status = "okay"; 348 }; 349 350 shdwc: shdwc@e001d010 { 351 compatible = "microchip,sama7g5-shdwc", "syscon"; 352 reg = <0xe001d010 0x10>; 353 clocks = <&clk32k 0>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 atmel,wakeup-rtc-timer; 357 atmel,wakeup-rtt-timer; 358 status = "disabled"; 359 secure-status = "okay"; 360 }; 361 362 rtt: rtc@e001d020 { 363 compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; 364 reg = <0xe001d020 0x30>; 365 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&clk32k 0>; 367 }; 368 369 clk32k: clock-controller@e001d050 { 370 compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; 371 reg = <0xe001d050 0x4>; 372 clocks = <&slow_xtal>; 373 #clock-cells = <1>; 374 status = "disabled"; 375 secure-status = "okay"; 376 }; 377 378 gpbr: gpbr@e001d060 { 379 compatible = "microchip,sama7g5-gpbr", "syscon"; 380 reg = <0xe001d060 0x48>; 381 }; 382 383 rtc: rtc@e001d0a8 { 384 compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc"; 385 reg = <0xe001d0a8 0x30>; 386 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&clk32k 1>; 388 status = "disabled"; 389 secure-status = "okay"; 390 }; 391 392 ps_wdt: watchdog@e001d180 { 393 compatible = "microchip,sama7g5-wdt"; 394 reg = <0xe001d180 0x24>; 395 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&clk32k 0>; 397 status = "disabled"; 398 secure-status = "okay"; 399 }; 400 401 chipid@e0020000 { 402 compatible = "microchip,sama7g5-chipid"; 403 reg = <0xe0020000 0x8>; 404 }; 405 406 tcb1: timer@e0800000 { 407 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 reg = <0xe0800000 0x100>; 411 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>; 413 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 414 status = "disabled"; 415 secure-status = "okay"; 416 }; 417 418 hsmc: hsmc@e0808000 { 419 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 420 reg = <0xe0808000 0x1000>; 421 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 423 #address-cells = <1>; 424 #size-cells = <1>; 425 ranges; 426 427 pmecc: ecc-engine@e0808070 { 428 compatible = "atmel,sama5d2-pmecc"; 429 reg = <0xe0808070 0x490>, 430 <0xe0808500 0x200>; 431 }; 432 }; 433 434 qspi0: spi@e080c000 { 435 compatible = "microchip,sama7g5-ospi"; 436 reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; 437 reg-names = "qspi_base", "qspi_mmap"; 438 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 439 dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, 440 <&dma0 AT91_XDMAC_DT_PERID(40)>; 441 dma-names = "tx", "rx"; 442 clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; 443 clock-names = "pclk", "gclk"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 status = "disabled"; 447 }; 448 449 qspi1: spi@e0810000 { 450 compatible = "microchip,sama7g5-qspi"; 451 reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; 452 reg-names = "qspi_base", "qspi_mmap"; 453 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 454 dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, 455 <&dma0 AT91_XDMAC_DT_PERID(42)>; 456 dma-names = "tx", "rx"; 457 clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; 458 clock-names = "pclk", "gclk"; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 status = "disabled"; 462 }; 463 464 can0: can@e0828000 { 465 compatible = "bosch,m_can"; 466 reg = <0xe0828000 0x100>, <0x100000 0x7800>; 467 reg-names = "m_can", "message_ram"; 468 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 469 GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 470 interrupt-names = "int0", "int1"; 471 clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; 472 clock-names = "hclk", "cclk"; 473 assigned-clocks = <&pmc PMC_TYPE_GCK 61>; 474 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 475 assigned-clock-rates = <40000000>; 476 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; 477 status = "disabled"; 478 }; 479 480 can1: can@e082c000 { 481 compatible = "bosch,m_can"; 482 reg = <0xe082c000 0x100>, <0x100000 0xbc00>; 483 reg-names = "m_can", "message_ram"; 484 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 485 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 486 interrupt-names = "int0", "int1"; 487 clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; 488 clock-names = "hclk", "cclk"; 489 assigned-clocks = <&pmc PMC_TYPE_GCK 62>; 490 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 491 assigned-clock-rates = <40000000>; 492 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; 493 status = "disabled"; 494 }; 495 496 can2: can@e0830000 { 497 compatible = "bosch,m_can"; 498 reg = <0xe0830000 0x100>, <0x100000 0x10000>; 499 reg-names = "m_can", "message_ram"; 500 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 501 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 502 interrupt-names = "int0", "int1"; 503 clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; 504 clock-names = "hclk", "cclk"; 505 assigned-clocks = <&pmc PMC_TYPE_GCK 63>; 506 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 507 assigned-clock-rates = <40000000>; 508 bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; 509 status = "disabled"; 510 }; 511 512 can3: can@e0834000 { 513 compatible = "bosch,m_can"; 514 reg = <0xe0834000 0x100>, <0x110000 0x4400>; 515 reg-names = "m_can", "message_ram"; 516 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 517 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 518 interrupt-names = "int0", "int1"; 519 clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; 520 clock-names = "hclk", "cclk"; 521 assigned-clocks = <&pmc PMC_TYPE_GCK 64>; 522 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 523 assigned-clock-rates = <40000000>; 524 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 525 status = "disabled"; 526 }; 527 528 can4: can@e0838000 { 529 compatible = "bosch,m_can"; 530 reg = <0xe0838000 0x100>, <0x110000 0x8800>; 531 reg-names = "m_can", "message_ram"; 532 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 533 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 534 interrupt-names = "int0", "int1"; 535 clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; 536 clock-names = "hclk", "cclk"; 537 assigned-clocks = <&pmc PMC_TYPE_GCK 65>; 538 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 539 assigned-clock-rates = <40000000>; 540 bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; 541 status = "disabled"; 542 }; 543 544 can5: can@e083c000 { 545 compatible = "bosch,m_can"; 546 reg = <0xe083c000 0x100>, <0x110000 0xcc00>; 547 reg-names = "m_can", "message_ram"; 548 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 549 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 550 interrupt-names = "int0", "int1"; 551 clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; 552 clock-names = "hclk", "cclk"; 553 assigned-clocks = <&pmc PMC_TYPE_GCK 66>; 554 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 555 assigned-clock-rates = <40000000>; 556 bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>; 557 status = "disabled"; 558 }; 559 560 adc: adc@e1000000 { 561 compatible = "microchip,sama7g5-adc"; 562 reg = <0xe1000000 0x200>; 563 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&pmc PMC_TYPE_GCK 26>; 565 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 566 assigned-clock-rates = <100000000>; 567 clock-names = "adc_clk"; 568 dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>; 569 dma-names = "rx"; 570 atmel,min-sample-rate-hz = <200000>; 571 atmel,max-sample-rate-hz = <20000000>; 572 atmel,startup-time-ms = <4>; 573 #io-channel-cells = <1>; 574 nvmem-cells = <&temperature_calib>; 575 nvmem-cell-names = "temperature_calib"; 576 status = "disabled"; 577 }; 578 579 sdmmc0: mmc@e1204000 { 580 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 581 reg = <0xe1204000 0x4000>; 582 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; 584 clock-names = "hclock", "multclk"; 585 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 586 assigned-clocks = <&pmc PMC_TYPE_GCK 80>; 587 assigned-clock-rates = <200000000>; 588 microchip,sdcal-inverted; 589 status = "disabled"; 590 }; 591 592 sdmmc1: mmc@e1208000 { 593 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 594 reg = <0xe1208000 0x4000>; 595 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; 597 clock-names = "hclock", "multclk"; 598 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 599 assigned-clocks = <&pmc PMC_TYPE_GCK 81>; 600 assigned-clock-rates = <200000000>; 601 microchip,sdcal-inverted; 602 status = "disabled"; 603 }; 604 605 sdmmc2: mmc@e120c000 { 606 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 607 reg = <0xe120c000 0x4000>; 608 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; 610 clock-names = "hclock", "multclk"; 611 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 612 assigned-clocks = <&pmc PMC_TYPE_GCK 82>; 613 assigned-clock-rates = <200000000>; 614 microchip,sdcal-inverted; 615 status = "disabled"; 616 }; 617 618 csi2host: csi2host@e1400000 { 619 compatible = "snps,dw-csi"; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 reg = <0xe1400000 0x7FF>; 623 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>, <&pmc PMC_TYPE_GCK 33>; 625 clock-names = "perclk", "phyclk"; 626 assigned-clocks = <&pmc PMC_TYPE_GCK 33>; 627 assigned-clock-rates = <26600000>; 628 snps,output-type = <1>; 629 phys = <&csi_dphy>; 630 status = "disabled"; 631 632 port@1 { 633 reg = <1>; 634 csi2host_in: endpoint { 635 }; 636 }; 637 638 port@2 { 639 reg = <2>; 640 csi2host_out: endpoint { 641 }; 642 }; 643 }; 644 645 csi_dphy: dphy@e1400040 { 646 compatible = "snps,dw-dphy-rx"; 647 #phy-cells = <0>; 648 bus-width = <8>; 649 snps,dphy-frequency = <900000>; 650 snps,phy_type = <0>; 651 reg = <0xe1400040 0x20>; 652 status = "disabled"; 653 }; 654 655 csi2dc: csi2dc@e1404000 { 656 compatible = "microchip,sama7g5-csi2dc"; 657 reg = <0xe1404000 0x500>; 658 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; 659 clock-names = "pclk", "scck"; 660 assigned-clocks = <&xisc>; 661 assigned-clock-rates = <266000000>; 662 status = "disabled"; 663 664 ports { 665 #address-cells = <1>; 666 #size-cells = <0>; 667 port@0 { 668 reg = <0>; 669 csi2dc_in: endpoint { 670 }; 671 }; 672 673 port@1 { 674 reg = <1>; 675 csi2dc_out: endpoint { 676 bus-width = <14>; 677 hsync-active = <1>; 678 vsync-active = <1>; 679 remote-endpoint = <&xisc_in>; 680 }; 681 }; 682 }; 683 }; 684 685 xisc: xisc@e1408000 { 686 compatible = "microchip,sama7g5-isc"; 687 reg = <0xe1408000 0x2000>; 688 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; 690 clock-names = "hclock"; 691 #clock-cells = <0>; 692 clock-output-names = "isc-mck"; 693 status = "disabled"; 694 695 port { 696 xisc_in: endpoint { 697 bus-type = <5>; /* Parallel */ 698 bus-width = <14>; 699 hsync-active = <1>; 700 vsync-active = <1>; 701 remote-endpoint = <&csi2dc_out>; 702 }; 703 }; 704 }; 705 706 pwm: pwm@e1604000 { 707 compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; 708 reg = <0xe1604000 0x4000>; 709 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 710 #pwm-cells = <3>; 711 clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; 712 status = "disabled"; 713 }; 714 715 pdmc0: sound@e1608000 { 716 compatible = "microchip,sama7g5-pdmc"; 717 reg = <0xe1608000 0x1000>; 718 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 719 #sound-dai-cells = <0>; 720 dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>; 721 dma-names = "rx"; 722 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>; 723 clock-names = "pclk", "gclk"; 724 sound-name-prefix = "PDMC0"; 725 status = "disabled"; 726 }; 727 728 pdmc1: sound@e160c000 { 729 compatible = "microchip,sama7g5-pdmc"; 730 reg = <0xe160c000 0x1000>; 731 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 732 #sound-dai-cells = <0>; 733 dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>; 734 dma-names = "rx"; 735 clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>; 736 clock-names = "pclk", "gclk"; 737 sound-name-prefix = "PDMC1"; 738 status = "disabled"; 739 }; 740 741 asrc: sound@e1610000 { 742 compatible = "microchip,sama7g5-asrc"; 743 reg = <0xe1610000 0x1000>; 744 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 745 #sound-dai-cells = <1>; 746 dmas = <&dma0 AT91_XDMAC_DT_PERID(55)>, 747 <&dma0 AT91_XDMAC_DT_PERID(56)>, 748 <&dma0 AT91_XDMAC_DT_PERID(57)>, 749 <&dma0 AT91_XDMAC_DT_PERID(58)>, 750 <&dma0 AT91_XDMAC_DT_PERID(59)>, 751 <&dma0 AT91_XDMAC_DT_PERID(60)>, 752 <&dma0 AT91_XDMAC_DT_PERID(61)>, 753 <&dma0 AT91_XDMAC_DT_PERID(62)>; 754 dma-names = "rx0", "tx0", "rx1", "tx1", 755 "rx2", "tx2", "rx3", "tx3"; 756 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; 757 clock-names = "pclk", "gclk"; 758 microchip,triggers = <&i2s0>, <&i2s1>, <&pdmc0>, <&pdmc1>, 759 <&ssc0>, <&ssc1>, <&spdiftx>, <&spdifrx>; 760 microchip,trigger-indexes = <1>, <2>, <3>, <4>, <5>, <8>, <9>, <10>; 761 assigned-clocks = <&pmc PMC_TYPE_GCK 30>; 762 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_AUDIOPMCPLL>; 763 status = "disabled"; 764 }; 765 766 spdifrx: spdifrx@e1614000 { 767 #sound-dai-cells = <0>; 768 compatible = "microchip,sama7g5-spdifrx"; 769 reg = <0xe1614000 0x4000>; 770 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 771 dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; 772 dma-names = "rx"; 773 clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; 774 clock-names = "pclk", "gclk"; 775 status = "disabled"; 776 sound-name-prefix = "SPDIFRX0"; 777 }; 778 779 spdiftx: spdiftx@e1618000 { 780 #sound-dai-cells = <0>; 781 compatible = "microchip,sama7g5-spdiftx"; 782 reg = <0xe1618000 0x4000>; 783 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 784 dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; 785 dma-names = "tx"; 786 clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; 787 clock-names = "pclk", "gclk"; 788 sound-name-prefix = "SPDIFTX0"; 789 }; 790 791 i2s0: i2s@e161c000 { 792 compatible = "microchip,sama7g5-i2smcc"; 793 #sound-dai-cells = <0>; 794 reg = <0xe161c000 0x4000>; 795 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 796 dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; 797 dma-names = "tx", "rx"; 798 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 799 clock-names = "pclk", "gclk"; 800 sound-name-prefix = "I2SMCC0"; 801 status = "disabled"; 802 }; 803 804 i2s1: i2s@e1620000 { 805 compatible = "microchip,sama7g5-i2smcc"; 806 #sound-dai-cells = <0>; 807 reg = <0xe1620000 0x4000>; 808 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 809 dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; 810 dma-names = "tx", "rx"; 811 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 812 clock-names = "pclk", "gclk"; 813 sound-name-prefix = "I2SMCC1"; 814 status = "disabled"; 815 }; 816 817 sfr: sfr@e1624000 { 818 compatible = "microchip,sama7g5-sfr", "syscon"; 819 reg = <0xe1624000 0x4000>; 820 }; 821 822 eic: interrupt-controller@e1628000 { 823 compatible = "microchip,sama7g5-eic"; 824 reg = <0xe1628000 0xec>; 825 interrupt-parent = <&gic>; 826 interrupt-controller; 827 #interrupt-cells = <2>; 828 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 831 clock-names = "pclk"; 832 status = "disabled"; 833 }; 834 835 pit64b0: timer@e1800000 { 836 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 837 reg = <0xe1800000 0x4000>; 838 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; 840 clock-names = "pclk", "gclk"; 841 }; 842 843 pit64b1: timer@e1804000 { 844 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 845 reg = <0xe1804000 0x4000>; 846 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; 848 clock-names = "pclk", "gclk"; 849 }; 850 851 ssc0: sound@e180c000 { 852 compatible = "atmel,at91sam9g45-ssc"; 853 reg = <0xe180c000 0x1000>; 854 #sound-dai-cells = <0>; 855 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 856 dmas = <&dma0 AT91_XDMAC_DT_PERID(44)>, 857 <&dma0 AT91_XDMAC_DT_PERID(45)>; 858 dma-names = "rx", "tx"; 859 clocks = <&pmc PMC_TYPE_PERIPHERAL 86>; 860 clock-names = "pclk"; 861 sound-name-prefix = "SSC0"; 862 status = "disabled"; 863 }; 864 865 aes: crypto@e1810000 { 866 compatible = "atmel,at91sam9g46-aes"; 867 reg = <0xe1810000 0x100>; 868 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 870 clock-names = "aes_clk"; 871 dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, 872 <&dma0 AT91_XDMAC_DT_PERID(2)>; 873 dma-names = "tx", "rx"; 874 status = "okay"; 875 }; 876 877 sha: crypto@e1814000 { 878 compatible = "atmel,at91sam9g46-sha"; 879 reg = <0xe1814000 0x100>; 880 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; 882 clock-names = "sha_clk"; 883 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; 884 dma-names = "tx"; 885 status = "okay"; 886 }; 887 888 flx0: flexcom@e1818000 { 889 compatible = "atmel,sama5d2-flexcom"; 890 reg = <0xe1818000 0x200>; 891 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 892 #address-cells = <1>; 893 #size-cells = <1>; 894 ranges = <0x0 0xe1818000 0x800>; 895 status = "disabled"; 896 897 uart0: serial@200 { 898 compatible = "atmel,at91sam9260-usart"; 899 reg = <0x200 0x200>; 900 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 902 clock-names = "usart"; 903 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, 904 <&dma1 AT91_XDMAC_DT_PERID(5)>; 905 dma-names = "tx", "rx"; 906 atmel,use-dma-rx; 907 atmel,use-dma-tx; 908 status = "disabled"; 909 }; 910 }; 911 912 flx1: flexcom@e181c000 { 913 compatible = "atmel,sama5d2-flexcom"; 914 reg = <0xe181c000 0x200>; 915 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 916 #address-cells = <1>; 917 #size-cells = <1>; 918 ranges = <0x0 0xe181c000 0x800>; 919 status = "disabled"; 920 921 i2c1: i2c@600 { 922 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 923 reg = <0x600 0x200>; 924 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 925 #address-cells = <1>; 926 #size-cells = <0>; 927 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 928 atmel,fifo-size = <32>; 929 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 930 <&dma0 AT91_XDMAC_DT_PERID(7)>; 931 dma-names = "tx", "rx"; 932 status = "disabled"; 933 }; 934 }; 935 936 flx3: flexcom@e1824000 { 937 compatible = "atmel,sama5d2-flexcom"; 938 reg = <0xe1824000 0x200>; 939 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 940 #address-cells = <1>; 941 #size-cells = <1>; 942 ranges = <0x0 0xe1824000 0x800>; 943 status = "disabled"; 944 945 uart3: serial@200 { 946 compatible = "atmel,at91sam9260-usart"; 947 reg = <0x200 0x200>; 948 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 949 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 950 clock-names = "usart"; 951 dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, 952 <&dma1 AT91_XDMAC_DT_PERID(11)>; 953 dma-names = "tx", "rx"; 954 atmel,use-dma-rx; 955 atmel,use-dma-tx; 956 status = "disabled"; 957 }; 958 }; 959 960 ssc1: sound@e200c000 { 961 compatible = "atmel,at91sam9g45-ssc"; 962 reg = <0xe200c000 0x1000>; 963 #sound-dai-cells = <0>; 964 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 965 dmas = <&dma0 AT91_XDMAC_DT_PERID(46)>, 966 <&dma0 AT91_XDMAC_DT_PERID(47)>; 967 dma-names = "rx", "tx"; 968 clocks = <&pmc PMC_TYPE_PERIPHERAL 87>; 969 clock-names = "pclk"; 970 sound-name-prefix = "SSC1"; 971 status = "disabled"; 972 }; 973 974 trng: rng@e2010000 { 975 compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; 976 reg = <0xe2010000 0x100>; 977 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; 979 status = "disabled"; 980 secure-status = "okay"; 981 }; 982 983 tdes: crypto@e2014000 { 984 compatible = "atmel,at91sam9g46-tdes"; 985 reg = <0xe2014000 0x100>; 986 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; 988 clock-names = "tdes_clk"; 989 dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, 990 <&dma0 AT91_XDMAC_DT_PERID(53)>; 991 dma-names = "tx", "rx"; 992 status = "okay"; 993 }; 994 995 flx4: flexcom@e2018000 { 996 compatible = "atmel,sama5d2-flexcom"; 997 reg = <0xe2018000 0x200>; 998 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 999 #address-cells = <1>; 1000 #size-cells = <1>; 1001 ranges = <0x0 0xe2018000 0x800>; 1002 status = "disabled"; 1003 1004 uart4: serial@200 { 1005 compatible = "atmel,at91sam9260-usart"; 1006 reg = <0x200 0x200>; 1007 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 1009 clock-names = "usart"; 1010 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, 1011 <&dma1 AT91_XDMAC_DT_PERID(13)>; 1012 dma-names = "tx", "rx"; 1013 atmel,use-dma-rx; 1014 atmel,use-dma-tx; 1015 atmel,fifo-size = <16>; 1016 status = "disabled"; 1017 }; 1018 }; 1019 1020 flx7: flexcom@e2024000 { 1021 compatible = "atmel,sama5d2-flexcom"; 1022 reg = <0xe2024000 0x200>; 1023 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 1024 #address-cells = <1>; 1025 #size-cells = <1>; 1026 ranges = <0x0 0xe2024000 0x800>; 1027 status = "disabled"; 1028 1029 uart7: serial@200 { 1030 compatible = "atmel,at91sam9260-usart"; 1031 reg = <0x200 0x200>; 1032 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 1034 clock-names = "usart"; 1035 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 1036 <&dma1 AT91_XDMAC_DT_PERID(19)>; 1037 dma-names = "tx", "rx"; 1038 atmel,use-dma-rx; 1039 atmel,use-dma-tx; 1040 atmel,fifo-size = <16>; 1041 status = "disabled"; 1042 }; 1043 }; 1044 1045 gmac0: ethernet@e2800000 { 1046 compatible = "microchip,sama7g5-gem"; 1047 reg = <0xe2800000 0x1000>; 1048 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 1049 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 1050 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 1051 GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 1052 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 1053 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; 1055 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 1056 assigned-clocks = <&pmc PMC_TYPE_GCK 51>; 1057 assigned-clock-rates = <125000000>; 1058 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_ETHPLL>; 1059 status = "disabled"; 1060 }; 1061 1062 gmac1: ethernet@e2804000 { 1063 compatible = "microchip,sama7g5-emac"; 1064 reg = <0xe2804000 0x1000>; 1065 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 1066 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_GCK 54>; 1068 clock-names = "pclk", "hclk", "tsu_clk"; 1069 assigned-clocks = <&pmc PMC_TYPE_GCK 54>; 1070 assigned-clock-rates = <200000000>; 1071 status = "disabled"; 1072 }; 1073 1074 dma0: dma-controller@e2808000 { 1075 compatible = "microchip,sama7g5-dma"; 1076 reg = <0xe2808000 0x1000>; 1077 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1078 #dma-cells = <1>; 1079 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 1080 clock-names = "dma_clk"; 1081 status = "disabled"; 1082 }; 1083 1084 dma1: dma-controller@e280c000 { 1085 compatible = "microchip,sama7g5-dma"; 1086 reg = <0xe280c000 0x1000>; 1087 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1088 #dma-cells = <1>; 1089 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 1090 clock-names = "dma_clk"; 1091 status = "disabled"; 1092 }; 1093 1094 /* Place dma2 here despite it's address */ 1095 dma2: dma-controller@e1200000 { 1096 compatible = "microchip,sama7g5-dma"; 1097 reg = <0xe1200000 0x1000>; 1098 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1099 #dma-cells = <1>; 1100 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 1101 clock-names = "dma_clk"; 1102 dma-requests = <0>; 1103 status = "disabled"; 1104 }; 1105 1106 tcb0: timer@e2814000 { 1107 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 reg = <0xe2814000 0x100>; 1111 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1112 clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>; 1113 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 1114 }; 1115 1116 flx8: flexcom@e2818000 { 1117 compatible = "atmel,sama5d2-flexcom"; 1118 reg = <0xe2818000 0x200>; 1119 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 1120 #address-cells = <1>; 1121 #size-cells = <1>; 1122 ranges = <0x0 0xe2818000 0x800>; 1123 status = "disabled"; 1124 1125 i2c8: i2c@600 { 1126 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 1127 reg = <0x600 0x200>; 1128 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 1132 atmel,fifo-size = <32>; 1133 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 1134 <&dma0 AT91_XDMAC_DT_PERID(21)>; 1135 dma-names = "tx", "rx"; 1136 status = "disabled"; 1137 }; 1138 }; 1139 1140 flx9: flexcom@e281c000 { 1141 compatible = "atmel,sama5d2-flexcom"; 1142 reg = <0xe281c000 0x200>; 1143 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1144 #address-cells = <1>; 1145 #size-cells = <1>; 1146 ranges = <0x0 0xe281c000 0x800>; 1147 status = "disabled"; 1148 1149 i2c9: i2c@600 { 1150 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 1151 reg = <0x600 0x200>; 1152 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1156 atmel,fifo-size = <32>; 1157 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 1158 <&dma0 AT91_XDMAC_DT_PERID(23)>; 1159 dma-names = "tx", "rx"; 1160 status = "disabled"; 1161 }; 1162 }; 1163 1164 flx11: flexcom@e2824000 { 1165 compatible = "atmel,sama5d2-flexcom"; 1166 reg = <0xe2824000 0x200>; 1167 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 1168 #address-cells = <1>; 1169 #size-cells = <1>; 1170 ranges = <0x0 0xe2824000 0x800>; 1171 status = "disabled"; 1172 1173 spi11: spi@400 { 1174 compatible = "atmel,at91rm9200-spi"; 1175 reg = <0x400 0x200>; 1176 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 1178 clock-names = "spi_clk"; 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 atmel,fifo-size = <32>; 1182 dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, 1183 <&dma0 AT91_XDMAC_DT_PERID(27)>; 1184 dma-names = "tx", "rx"; 1185 status = "disabled"; 1186 }; 1187 }; 1188 1189 uddrc: uddrc@e3800000 { 1190 compatible = "microchip,sama7g5-uddrc"; 1191 reg = <0xe3800000 0x4000>; 1192 }; 1193 1194 ddr3phy: ddr3phy@e3804000 { 1195 compatible = "microchip,sama7g5-ddr3phy"; 1196 reg = <0xe3804000 0x1000>; 1197 }; 1198 1199 otpc: efuse@e8c00000 { 1200 compatible = "microchip,sama7g5-otpc", "syscon"; 1201 reg = <0xe8c00000 0x100>; 1202 #address-cells = <1>; 1203 #size-cells = <1>; 1204 1205 temperature_calib: calib@1 { 1206 status = "disabled"; 1207 }; 1208 }; 1209 1210 gic: interrupt-controller@e8c11000 { 1211 compatible = "arm,cortex-a7-gic"; 1212 #interrupt-cells = <3>; 1213 #address-cells = <0>; 1214 interrupt-controller; 1215 reg = <0xe8c11000 0x1000>, 1216 <0xe8c12000 0x2000>; 1217 }; 1218 }; 1219}; 1220