1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9#include <dt-bindings/dma/at91.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Atmel SAMA5D2 family SoC"; 18 compatible = "atmel,sama5d2"; 19 interrupt-parent = <&aic>; 20 21 aliases { 22 serial0 = &uart1; 23 serial1 = &uart3; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a5"; 33 reg = <0>; 34 next-level-cache = <&L2>; 35 clocks = <&pmc PMC_TYPE_CORE PMC_MCK_PRES>; 36 clock-names = "cpu"; 37 }; 38 }; 39 40 pmu { 41 compatible = "arm,cortex-a5-pmu"; 42 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; 43 }; 44 45 etb@740000 { 46 compatible = "arm,coresight-etb10", "arm,primecell"; 47 reg = <0x740000 0x1000>; 48 49 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 50 clock-names = "apb_pclk"; 51 52 in-ports { 53 port { 54 etb_in: endpoint { 55 remote-endpoint = <&etm_out>; 56 }; 57 }; 58 }; 59 }; 60 61 etm@73c000 { 62 compatible = "arm,coresight-etm3x", "arm,primecell"; 63 reg = <0x73c000 0x1000>; 64 65 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 66 clock-names = "apb_pclk"; 67 68 out-ports { 69 port { 70 etm_out: endpoint { 71 remote-endpoint = <&etb_in>; 72 }; 73 }; 74 }; 75 }; 76 77 memory@20000000 { 78 device_type = "memory"; 79 reg = <0x20000000 0x20000000>; 80 }; 81 82 clocks { 83 slow_xtal: slow_xtal { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <0>; 87 }; 88 89 main_xtal: main_xtal { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <0>; 93 }; 94 }; 95 96 ns_sram: sram@200000 { 97 compatible = "atmel,sama5d2-sram", "mmio-sram"; 98 reg = <0x00200000 0x20000>; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 ranges = <0 0x00200000 0x20000>; 102 status = "disabled"; 103 secure-status = "okay"; 104 }; 105 106 ahb { 107 compatible = "simple-bus"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges; 111 112 nfc_sram: sram@100000 { 113 compatible = "mmio-sram"; 114 no-memory-wc; 115 reg = <0x00100000 0x2400>; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges = <0 0x00100000 0x2400>; 119 120 }; 121 122 usb0: gadget@300000 { 123 compatible = "atmel,sama5d3-udc"; 124 reg = <0x00300000 0x100000 125 0xfc02c000 0x400>; 126 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; 127 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 128 clock-names = "pclk", "hclk"; 129 status = "disabled"; 130 }; 131 132 usb1: ohci@400000 { 133 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 134 reg = <0x00400000 0x100000>; 135 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 136 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; 137 clock-names = "ohci_clk", "hclk", "uhpck"; 138 status = "disabled"; 139 }; 140 141 usb2: ehci@500000 { 142 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 143 reg = <0x00500000 0x100000>; 144 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 145 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; 146 clock-names = "usb_clk", "ehci_clk"; 147 status = "disabled"; 148 }; 149 150 L2: cache-controller@a00000 { 151 compatible = "arm,pl310-cache"; 152 reg = <0x00a00000 0x1000>; 153 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; 154 cache-unified; 155 cache-level = <2>; 156 }; 157 158 ebi: ebi@10000000 { 159 compatible = "atmel,sama5d3-ebi"; 160 #address-cells = <2>; 161 #size-cells = <1>; 162 atmel,smc = <&hsmc>; 163 reg = <0x10000000 0x10000000 164 0x60000000 0x30000000>; 165 ranges = <0x0 0x0 0x10000000 0x10000000 166 0x1 0x0 0x60000000 0x10000000 167 0x2 0x0 0x70000000 0x10000000 168 0x3 0x0 0x80000000 0x10000000>; 169 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 170 status = "disabled"; 171 172 nand_controller: nand-controller { 173 compatible = "atmel,sama5d3-nand-controller"; 174 atmel,nfc-sram = <&nfc_sram>; 175 atmel,nfc-io = <&nfc_io>; 176 ecc-engine = <&pmecc>; 177 #address-cells = <2>; 178 #size-cells = <1>; 179 ranges; 180 status = "disabled"; 181 }; 182 }; 183 184 sdmmc0: sdio-host@a0000000 { 185 compatible = "atmel,sama5d2-sdhci"; 186 reg = <0xa0000000 0x300>; 187 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 188 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 189 clock-names = "hclock", "multclk", "baseclk"; 190 assigned-clocks = <&pmc PMC_TYPE_GCK 31>; 191 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 192 assigned-clock-rates = <480000000>; 193 status = "disabled"; 194 }; 195 196 sdmmc1: sdio-host@b0000000 { 197 compatible = "atmel,sama5d2-sdhci"; 198 reg = <0xb0000000 0x300>; 199 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; 200 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 201 clock-names = "hclock", "multclk", "baseclk"; 202 assigned-clocks = <&pmc PMC_TYPE_GCK 32>; 203 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 204 assigned-clock-rates = <480000000>; 205 status = "disabled"; 206 }; 207 208 nfc_io: nfc-io@c0000000 { 209 compatible = "atmel,sama5d3-nfc-io", "syscon"; 210 reg = <0xc0000000 0x8000000>; 211 }; 212 213 apb { 214 compatible = "simple-bus"; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges; 218 219 hlcdc: hlcdc@f0000000 { 220 compatible = "atmel,sama5d2-hlcdc"; 221 reg = <0xf0000000 0x2000>; 222 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 223 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 224 clock-names = "periph_clk","sys_clk", "slow_clk"; 225 status = "disabled"; 226 227 hlcdc-display-controller { 228 compatible = "atmel,hlcdc-display-controller"; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 232 port@0 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 reg = <0>; 236 }; 237 }; 238 239 hlcdc_pwm: hlcdc-pwm { 240 compatible = "atmel,hlcdc-pwm"; 241 #pwm-cells = <3>; 242 }; 243 }; 244 245 isc: isc@f0008000 { 246 compatible = "atmel,sama5d2-isc"; 247 reg = <0xf0008000 0x4000>; 248 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; 249 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; 250 clock-names = "hclock", "iscck", "gck"; 251 #clock-cells = <0>; 252 clock-output-names = "isc-mck"; 253 status = "disabled"; 254 }; 255 256 ramc0: ramc@f000c000 { 257 compatible = "atmel,sama5d3-ddramc"; 258 reg = <0xf000c000 0x200>; 259 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; 260 clock-names = "ddrck", "mpddr"; 261 }; 262 263 dma0: dma-controller@f0010000 { 264 compatible = "atmel,sama5d4-dma"; 265 reg = <0xf0010000 0x1000>; 266 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 267 #dma-cells = <1>; 268 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 269 clock-names = "dma_clk"; 270 }; 271 272 /* Place dma1 here despite its address */ 273 dma1: dma-controller@f0004000 { 274 compatible = "atmel,sama5d4-dma"; 275 reg = <0xf0004000 0x1000>; 276 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; 277 #dma-cells = <1>; 278 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 279 clock-names = "dma_clk"; 280 }; 281 282 pmc: pmc@f0014000 { 283 compatible = "atmel,sama5d2-pmc", "syscon"; 284 reg = <0xf0014000 0x160>; 285 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 286 #clock-cells = <2>; 287 clocks = <&clk32k>, <&main_xtal>; 288 clock-names = "slow_clk", "main_xtal"; 289 }; 290 291 qspi0: spi@f0020000 { 292 compatible = "atmel,sama5d2-qspi"; 293 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; 294 reg-names = "qspi_base", "qspi_mmap"; 295 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; 296 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 status = "disabled"; 300 }; 301 302 qspi1: spi@f0024000 { 303 compatible = "atmel,sama5d2-qspi"; 304 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; 305 reg-names = "qspi_base", "qspi_mmap"; 306 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; 307 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 status = "disabled"; 311 }; 312 313 sha@f0028000 { 314 compatible = "atmel,at91sam9g46-sha"; 315 reg = <0xf0028000 0x100>; 316 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 317 dmas = <&dma0 318 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 319 AT91_XDMAC_DT_PERID(30))>; 320 dma-names = "tx"; 321 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 322 clock-names = "sha_clk"; 323 status = "okay"; 324 }; 325 326 aes@f002c000 { 327 compatible = "atmel,at91sam9g46-aes"; 328 reg = <0xf002c000 0x100>; 329 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 330 dmas = <&dma0 331 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 332 AT91_XDMAC_DT_PERID(26))>, 333 <&dma0 334 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 335 AT91_XDMAC_DT_PERID(27))>; 336 dma-names = "tx", "rx"; 337 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 338 clock-names = "aes_clk"; 339 status = "okay"; 340 }; 341 342 spi0: spi@f8000000 { 343 compatible = "atmel,at91rm9200-spi"; 344 reg = <0xf8000000 0x100>; 345 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 346 dmas = <&dma0 347 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 348 AT91_XDMAC_DT_PERID(6))>, 349 <&dma0 350 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 351 AT91_XDMAC_DT_PERID(7))>; 352 dma-names = "tx", "rx"; 353 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 354 clock-names = "spi_clk"; 355 atmel,fifo-size = <16>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 status = "disabled"; 359 }; 360 361 ssc0: ssc@f8004000 { 362 compatible = "atmel,at91sam9g45-ssc"; 363 reg = <0xf8004000 0x4000>; 364 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 365 dmas = <&dma0 366 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 367 AT91_XDMAC_DT_PERID(21))>, 368 <&dma0 369 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 370 AT91_XDMAC_DT_PERID(22))>; 371 dma-names = "tx", "rx"; 372 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 373 clock-names = "pclk"; 374 status = "disabled"; 375 }; 376 377 macb0: ethernet@f8008000 { 378 compatible = "atmel,sama5d2-gem"; 379 reg = <0xf8008000 0x1000>; 380 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ 381 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ 382 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ 383 #address-cells = <1>; 384 #size-cells = <0>; 385 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; 386 clock-names = "hclk", "pclk"; 387 status = "disabled"; 388 }; 389 390 tcb0: timer@f800c000 { 391 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 reg = <0xf800c000 0x100>; 395 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 396 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; 397 clock-names = "t0_clk", "gclk", "slow_clk"; 398 }; 399 400 tcb1: timer@f8010000 { 401 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 reg = <0xf8010000 0x100>; 405 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 406 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; 407 clock-names = "t0_clk", "gclk", "slow_clk"; 408 }; 409 410 hsmc: hsmc@f8014000 { 411 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 412 reg = <0xf8014000 0x1000>; 413 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; 414 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 415 #address-cells = <1>; 416 #size-cells = <1>; 417 ranges; 418 419 pmecc: ecc-engine@f8014070 { 420 compatible = "atmel,sama5d2-pmecc"; 421 reg = <0xf8014070 0x490>, 422 <0xf8014500 0x100>; 423 }; 424 }; 425 426 pdmic: pdmic@f8018000 { 427 compatible = "atmel,sama5d2-pdmic"; 428 reg = <0xf8018000 0x124>; 429 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; 430 dmas = <&dma0 431 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 432 | AT91_XDMAC_DT_PERID(50))>; 433 dma-names = "rx"; 434 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; 435 clock-names = "pclk", "gclk"; 436 status = "disabled"; 437 }; 438 439 uart0: serial@f801c000 { 440 compatible = "atmel,at91sam9260-usart"; 441 reg = <0xf801c000 0x100>; 442 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; 443 dmas = <&dma0 444 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 445 AT91_XDMAC_DT_PERID(35))>, 446 <&dma0 447 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 448 AT91_XDMAC_DT_PERID(36))>; 449 dma-names = "tx", "rx"; 450 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 451 clock-names = "usart"; 452 status = "disabled"; 453 }; 454 455 uart1: serial@f8020000 { 456 compatible = "atmel,at91sam9260-usart"; 457 reg = <0xf8020000 0x100>; 458 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; 459 dmas = <&dma0 460 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 461 AT91_XDMAC_DT_PERID(37))>, 462 <&dma0 463 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 464 AT91_XDMAC_DT_PERID(38))>; 465 dma-names = "tx", "rx"; 466 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 467 clock-names = "usart"; 468 status = "disabled"; 469 }; 470 471 uart2: serial@f8024000 { 472 compatible = "atmel,at91sam9260-usart"; 473 reg = <0xf8024000 0x100>; 474 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; 475 dmas = <&dma0 476 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 477 AT91_XDMAC_DT_PERID(39))>, 478 <&dma0 479 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 480 AT91_XDMAC_DT_PERID(40))>; 481 dma-names = "tx", "rx"; 482 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 483 clock-names = "usart"; 484 status = "disabled"; 485 }; 486 487 i2c0: i2c@f8028000 { 488 compatible = "atmel,sama5d2-i2c"; 489 reg = <0xf8028000 0x100>; 490 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; 491 dmas = <&dma0 492 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 493 AT91_XDMAC_DT_PERID(0))>, 494 <&dma0 495 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 496 AT91_XDMAC_DT_PERID(1))>; 497 dma-names = "tx", "rx"; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 501 atmel,fifo-size = <16>; 502 status = "disabled"; 503 }; 504 505 pwm0: pwm@f802c000 { 506 compatible = "atmel,sama5d2-pwm"; 507 reg = <0xf802c000 0x4000>; 508 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; 509 #pwm-cells = <3>; 510 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 511 status = "disabled"; 512 }; 513 514 sfr: sfr@f8030000 { 515 compatible = "atmel,sama5d2-sfr", "syscon"; 516 reg = <0xf8030000 0x98>; 517 }; 518 519 flx0: flexcom@f8034000 { 520 compatible = "atmel,sama5d2-flexcom"; 521 reg = <0xf8034000 0x200>; 522 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 523 #address-cells = <1>; 524 #size-cells = <1>; 525 ranges = <0x0 0xf8034000 0x800>; 526 status = "disabled"; 527 528 uart5: serial@200 { 529 compatible = "atmel,at91sam9260-usart"; 530 reg = <0x200 0x200>; 531 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 532 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 533 clock-names = "usart"; 534 dmas = <&dma0 535 (AT91_XDMAC_DT_MEM_IF(0) | 536 AT91_XDMAC_DT_PER_IF(1) | 537 AT91_XDMAC_DT_PERID(11))>, 538 <&dma0 539 (AT91_XDMAC_DT_MEM_IF(0) | 540 AT91_XDMAC_DT_PER_IF(1) | 541 AT91_XDMAC_DT_PERID(12))>; 542 dma-names = "tx", "rx"; 543 atmel,fifo-size = <32>; 544 status = "disabled"; 545 }; 546 547 spi2: spi@400 { 548 compatible = "atmel,at91rm9200-spi"; 549 reg = <0x400 0x200>; 550 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 554 clock-names = "spi_clk"; 555 dmas = <&dma0 556 (AT91_XDMAC_DT_MEM_IF(0) | 557 AT91_XDMAC_DT_PER_IF(1) | 558 AT91_XDMAC_DT_PERID(11))>, 559 <&dma0 560 (AT91_XDMAC_DT_MEM_IF(0) | 561 AT91_XDMAC_DT_PER_IF(1) | 562 AT91_XDMAC_DT_PERID(12))>; 563 dma-names = "tx", "rx"; 564 atmel,fifo-size = <16>; 565 status = "disabled"; 566 }; 567 568 i2c2: i2c@600 { 569 compatible = "atmel,sama5d2-i2c"; 570 reg = <0x600 0x200>; 571 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 575 dmas = <&dma0 576 (AT91_XDMAC_DT_MEM_IF(0) | 577 AT91_XDMAC_DT_PER_IF(1) | 578 AT91_XDMAC_DT_PERID(11))>, 579 <&dma0 580 (AT91_XDMAC_DT_MEM_IF(0) | 581 AT91_XDMAC_DT_PER_IF(1) | 582 AT91_XDMAC_DT_PERID(12))>; 583 dma-names = "tx", "rx"; 584 atmel,fifo-size = <16>; 585 status = "disabled"; 586 }; 587 }; 588 589 flx1: flexcom@f8038000 { 590 compatible = "atmel,sama5d2-flexcom"; 591 reg = <0xf8038000 0x200>; 592 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 593 #address-cells = <1>; 594 #size-cells = <1>; 595 ranges = <0x0 0xf8038000 0x800>; 596 status = "disabled"; 597 598 uart6: serial@200 { 599 compatible = "atmel,at91sam9260-usart"; 600 reg = <0x200 0x200>; 601 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 602 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 603 clock-names = "usart"; 604 dmas = <&dma0 605 (AT91_XDMAC_DT_MEM_IF(0) | 606 AT91_XDMAC_DT_PER_IF(1) | 607 AT91_XDMAC_DT_PERID(13))>, 608 <&dma0 609 (AT91_XDMAC_DT_MEM_IF(0) | 610 AT91_XDMAC_DT_PER_IF(1) | 611 AT91_XDMAC_DT_PERID(14))>; 612 dma-names = "tx", "rx"; 613 atmel,fifo-size = <32>; 614 status = "disabled"; 615 }; 616 617 spi3: spi@400 { 618 compatible = "atmel,at91rm9200-spi"; 619 reg = <0x400 0x200>; 620 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 624 clock-names = "spi_clk"; 625 dmas = <&dma0 626 (AT91_XDMAC_DT_MEM_IF(0) | 627 AT91_XDMAC_DT_PER_IF(1) | 628 AT91_XDMAC_DT_PERID(13))>, 629 <&dma0 630 (AT91_XDMAC_DT_MEM_IF(0) | 631 AT91_XDMAC_DT_PER_IF(1) | 632 AT91_XDMAC_DT_PERID(14))>; 633 dma-names = "tx", "rx"; 634 atmel,fifo-size = <16>; 635 status = "disabled"; 636 }; 637 638 i2c3: i2c@600 { 639 compatible = "atmel,sama5d2-i2c"; 640 reg = <0x600 0x200>; 641 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 645 dmas = <&dma0 646 (AT91_XDMAC_DT_MEM_IF(0) | 647 AT91_XDMAC_DT_PER_IF(1) | 648 AT91_XDMAC_DT_PERID(13))>, 649 <&dma0 650 (AT91_XDMAC_DT_MEM_IF(0) | 651 AT91_XDMAC_DT_PER_IF(1) | 652 AT91_XDMAC_DT_PERID(14))>; 653 dma-names = "tx", "rx"; 654 atmel,fifo-size = <16>; 655 status = "disabled"; 656 }; 657 }; 658 659 securam: sram@f8044000 { 660 compatible = "atmel,sama5d2-securam", "mmio-sram"; 661 reg = <0xf8044000 0x1420>; 662 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; 663 #address-cells = <1>; 664 #size-cells = <1>; 665 no-memory-wc; 666 ranges = <0 0xf8044000 0x1420>; 667 status = "disabled"; 668 secure-status = "okay"; 669 }; 670 671 reset_controller: rstc@f8048000 { 672 compatible = "atmel,sama5d3-rstc"; 673 reg = <0xf8048000 0x10>; 674 clocks = <&clk32k>; 675 }; 676 677 shutdown_controller: shdwc@f8048010 { 678 compatible = "atmel,sama5d2-shdwc"; 679 reg = <0xf8048010 0x10>; 680 clocks = <&clk32k>; 681 #address-cells = <1>; 682 #size-cells = <0>; 683 atmel,wakeup-rtc-timer; 684 }; 685 686 pit: timer@f8048030 { 687 compatible = "atmel,at91sam9260-pit"; 688 reg = <0xf8048030 0x10>; 689 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 690 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 691 }; 692 693 watchdog: watchdog@f8048040 { 694 compatible = "atmel,sama5d4-wdt"; 695 reg = <0xf8048040 0x10>; 696 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 697 clocks = <&clk32k>; 698 status = "disabled"; 699 secure-status = "okay"; 700 }; 701 702 clk32k: sckc@f8048050 { 703 compatible = "atmel,sama5d4-sckc"; 704 reg = <0xf8048050 0x4>; 705 706 clocks = <&slow_xtal>; 707 #clock-cells = <0>; 708 }; 709 710 rtc: rtc@f80480b0 { 711 compatible = "atmel,sama5d2-rtc"; 712 reg = <0xf80480b0 0x30>; 713 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 714 clocks = <&clk32k>; 715 status = "disabled"; 716 secure-status = "okay"; 717 }; 718 719 i2s0: i2s@f8050000 { 720 compatible = "atmel,sama5d2-i2s"; 721 reg = <0xf8050000 0x100>; 722 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; 723 dmas = <&dma0 724 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 725 AT91_XDMAC_DT_PERID(31))>, 726 <&dma0 727 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 728 AT91_XDMAC_DT_PERID(32))>; 729 dma-names = "tx", "rx"; 730 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; 731 clock-names = "pclk", "gclk"; 732 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; 733 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; 734 status = "disabled"; 735 }; 736 737 can0: can@f8054000 { 738 compatible = "bosch,m_can"; 739 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; 740 reg-names = "m_can", "message_ram"; 741 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, 742 <64 IRQ_TYPE_LEVEL_HIGH 7>; 743 interrupt-names = "int0", "int1"; 744 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; 745 clock-names = "hclk", "cclk"; 746 assigned-clocks = <&pmc PMC_TYPE_GCK 56>; 747 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 748 assigned-clock-rates = <40000000>; 749 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 750 status = "disabled"; 751 }; 752 753 spi1: spi@fc000000 { 754 compatible = "atmel,at91rm9200-spi"; 755 reg = <0xfc000000 0x100>; 756 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 757 dmas = <&dma0 758 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 759 AT91_XDMAC_DT_PERID(8))>, 760 <&dma0 761 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 762 AT91_XDMAC_DT_PERID(9))>; 763 dma-names = "tx", "rx"; 764 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 765 clock-names = "spi_clk"; 766 atmel,fifo-size = <16>; 767 #address-cells = <1>; 768 #size-cells = <0>; 769 status = "disabled"; 770 }; 771 772 uart3: serial@fc008000 { 773 compatible = "atmel,at91sam9260-usart"; 774 reg = <0xfc008000 0x100>; 775 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; 776 dmas = <&dma1 777 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 778 AT91_XDMAC_DT_PERID(41))>, 779 <&dma1 780 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 781 AT91_XDMAC_DT_PERID(42))>; 782 dma-names = "tx", "rx"; 783 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 784 clock-names = "usart"; 785 status = "disabled"; 786 }; 787 788 uart4: serial@fc00c000 { 789 compatible = "atmel,at91sam9260-usart"; 790 reg = <0xfc00c000 0x100>; 791 dmas = <&dma0 792 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 793 AT91_XDMAC_DT_PERID(43))>, 794 <&dma0 795 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 796 AT91_XDMAC_DT_PERID(44))>; 797 dma-names = "tx", "rx"; 798 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; 799 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 800 clock-names = "usart"; 801 status = "disabled"; 802 }; 803 804 flx2: flexcom@fc010000 { 805 compatible = "atmel,sama5d2-flexcom"; 806 reg = <0xfc010000 0x200>; 807 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 808 #address-cells = <1>; 809 #size-cells = <1>; 810 ranges = <0x0 0xfc010000 0x800>; 811 status = "disabled"; 812 813 uart7: serial@200 { 814 compatible = "atmel,at91sam9260-usart"; 815 reg = <0x200 0x200>; 816 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 817 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 818 clock-names = "usart"; 819 dmas = <&dma0 820 (AT91_XDMAC_DT_MEM_IF(0) | 821 AT91_XDMAC_DT_PER_IF(1) | 822 AT91_XDMAC_DT_PERID(15))>, 823 <&dma0 824 (AT91_XDMAC_DT_MEM_IF(0) | 825 AT91_XDMAC_DT_PER_IF(1) | 826 AT91_XDMAC_DT_PERID(16))>; 827 dma-names = "tx", "rx"; 828 atmel,fifo-size = <32>; 829 status = "disabled"; 830 }; 831 832 spi4: spi@400 { 833 compatible = "atmel,at91rm9200-spi"; 834 reg = <0x400 0x200>; 835 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 839 clock-names = "spi_clk"; 840 dmas = <&dma0 841 (AT91_XDMAC_DT_MEM_IF(0) | 842 AT91_XDMAC_DT_PER_IF(1) | 843 AT91_XDMAC_DT_PERID(15))>, 844 <&dma0 845 (AT91_XDMAC_DT_MEM_IF(0) | 846 AT91_XDMAC_DT_PER_IF(1) | 847 AT91_XDMAC_DT_PERID(16))>; 848 dma-names = "tx", "rx"; 849 atmel,fifo-size = <16>; 850 status = "disabled"; 851 }; 852 853 i2c4: i2c@600 { 854 compatible = "atmel,sama5d2-i2c"; 855 reg = <0x600 0x200>; 856 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 857 #address-cells = <1>; 858 #size-cells = <0>; 859 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 860 dmas = <&dma0 861 (AT91_XDMAC_DT_MEM_IF(0) | 862 AT91_XDMAC_DT_PER_IF(1) | 863 AT91_XDMAC_DT_PERID(15))>, 864 <&dma0 865 (AT91_XDMAC_DT_MEM_IF(0) | 866 AT91_XDMAC_DT_PER_IF(1) | 867 AT91_XDMAC_DT_PERID(16))>; 868 dma-names = "tx", "rx"; 869 atmel,fifo-size = <16>; 870 status = "disabled"; 871 }; 872 }; 873 874 flx3: flexcom@fc014000 { 875 compatible = "atmel,sama5d2-flexcom"; 876 reg = <0xfc014000 0x200>; 877 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 878 #address-cells = <1>; 879 #size-cells = <1>; 880 ranges = <0x0 0xfc014000 0x800>; 881 status = "disabled"; 882 883 uart8: serial@200 { 884 compatible = "atmel,at91sam9260-usart"; 885 reg = <0x200 0x200>; 886 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 887 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 888 clock-names = "usart"; 889 dmas = <&dma0 890 (AT91_XDMAC_DT_MEM_IF(0) | 891 AT91_XDMAC_DT_PER_IF(1) | 892 AT91_XDMAC_DT_PERID(17))>, 893 <&dma0 894 (AT91_XDMAC_DT_MEM_IF(0) | 895 AT91_XDMAC_DT_PER_IF(1) | 896 AT91_XDMAC_DT_PERID(18))>; 897 dma-names = "tx", "rx"; 898 atmel,fifo-size = <32>; 899 status = "disabled"; 900 }; 901 902 spi5: spi@400 { 903 compatible = "atmel,at91rm9200-spi"; 904 reg = <0x400 0x200>; 905 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 909 clock-names = "spi_clk"; 910 dmas = <&dma0 911 (AT91_XDMAC_DT_MEM_IF(0) | 912 AT91_XDMAC_DT_PER_IF(1) | 913 AT91_XDMAC_DT_PERID(17))>, 914 <&dma0 915 (AT91_XDMAC_DT_MEM_IF(0) | 916 AT91_XDMAC_DT_PER_IF(1) | 917 AT91_XDMAC_DT_PERID(18))>; 918 dma-names = "tx", "rx"; 919 atmel,fifo-size = <16>; 920 status = "disabled"; 921 }; 922 923 i2c5: i2c@600 { 924 compatible = "atmel,sama5d2-i2c"; 925 reg = <0x600 0x200>; 926 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 930 dmas = <&dma0 931 (AT91_XDMAC_DT_MEM_IF(0) | 932 AT91_XDMAC_DT_PER_IF(1) | 933 AT91_XDMAC_DT_PERID(17))>, 934 <&dma0 935 (AT91_XDMAC_DT_MEM_IF(0) | 936 AT91_XDMAC_DT_PER_IF(1) | 937 AT91_XDMAC_DT_PERID(18))>; 938 dma-names = "tx", "rx"; 939 atmel,fifo-size = <16>; 940 status = "disabled"; 941 }; 942 943 }; 944 945 flx4: flexcom@fc018000 { 946 compatible = "atmel,sama5d2-flexcom"; 947 reg = <0xfc018000 0x200>; 948 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 949 #address-cells = <1>; 950 #size-cells = <1>; 951 ranges = <0x0 0xfc018000 0x800>; 952 status = "disabled"; 953 954 uart9: serial@200 { 955 compatible = "atmel,at91sam9260-usart"; 956 reg = <0x200 0x200>; 957 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 958 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 959 clock-names = "usart"; 960 dmas = <&dma0 961 (AT91_XDMAC_DT_MEM_IF(0) | 962 AT91_XDMAC_DT_PER_IF(1) | 963 AT91_XDMAC_DT_PERID(19))>, 964 <&dma0 965 (AT91_XDMAC_DT_MEM_IF(0) | 966 AT91_XDMAC_DT_PER_IF(1) | 967 AT91_XDMAC_DT_PERID(20))>; 968 dma-names = "tx", "rx"; 969 atmel,fifo-size = <32>; 970 status = "disabled"; 971 }; 972 973 spi6: spi@400 { 974 compatible = "atmel,at91rm9200-spi"; 975 reg = <0x400 0x200>; 976 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 977 #address-cells = <1>; 978 #size-cells = <0>; 979 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 980 clock-names = "spi_clk"; 981 dmas = <&dma0 982 (AT91_XDMAC_DT_MEM_IF(0) | 983 AT91_XDMAC_DT_PER_IF(1) | 984 AT91_XDMAC_DT_PERID(19))>, 985 <&dma0 986 (AT91_XDMAC_DT_MEM_IF(0) | 987 AT91_XDMAC_DT_PER_IF(1) | 988 AT91_XDMAC_DT_PERID(20))>; 989 dma-names = "tx", "rx"; 990 atmel,fifo-size = <16>; 991 status = "disabled"; 992 }; 993 994 i2c6: i2c@600 { 995 compatible = "atmel,sama5d2-i2c"; 996 reg = <0x600 0x200>; 997 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 1001 dmas = <&dma0 1002 (AT91_XDMAC_DT_MEM_IF(0) | 1003 AT91_XDMAC_DT_PER_IF(1) | 1004 AT91_XDMAC_DT_PERID(19))>, 1005 <&dma0 1006 (AT91_XDMAC_DT_MEM_IF(0) | 1007 AT91_XDMAC_DT_PER_IF(1) | 1008 AT91_XDMAC_DT_PERID(20))>; 1009 dma-names = "tx", "rx"; 1010 atmel,fifo-size = <16>; 1011 status = "disabled"; 1012 }; 1013 }; 1014 1015 trng@fc01c000 { 1016 compatible = "atmel,at91sam9g45-trng"; 1017 reg = <0xfc01c000 0x100>; 1018 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; 1019 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1020 status = "disabled"; 1021 secure-status = "okay"; 1022 }; 1023 1024 aic: interrupt-controller@fc020000 { 1025 #interrupt-cells = <3>; 1026 compatible = "atmel,sama5d2-aic"; 1027 interrupt-controller; 1028 reg = <0xfc020000 0x200>; 1029 atmel,external-irqs = <49>; 1030 }; 1031 1032 saic: interrupt-controller@f803c000 { 1033 #interrupt-cells = <3>; 1034 compatible = "atmel,sama5d2-saic"; 1035 interrupt-controller; 1036 reg = <0xf803c000 0x200>; 1037 atmel,external-irqs = <49>; 1038 status = "disabled"; 1039 secure-status = "okay"; 1040 }; 1041 1042 i2c1: i2c@fc028000 { 1043 compatible = "atmel,sama5d2-i2c"; 1044 reg = <0xfc028000 0x100>; 1045 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; 1046 dmas = <&dma0 1047 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1048 AT91_XDMAC_DT_PERID(2))>, 1049 <&dma0 1050 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1051 AT91_XDMAC_DT_PERID(3))>; 1052 dma-names = "tx", "rx"; 1053 #address-cells = <1>; 1054 #size-cells = <0>; 1055 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 1056 atmel,fifo-size = <16>; 1057 status = "disabled"; 1058 }; 1059 1060 adc: adc@fc030000 { 1061 compatible = "atmel,sama5d2-adc"; 1062 reg = <0xfc030000 0x100>; 1063 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; 1064 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 1065 clock-names = "adc_clk"; 1066 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; 1067 dma-names = "rx"; 1068 atmel,min-sample-rate-hz = <200000>; 1069 atmel,max-sample-rate-hz = <20000000>; 1070 atmel,startup-time-ms = <4>; 1071 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1072 #io-channel-cells = <1>; 1073 status = "disabled"; 1074 }; 1075 1076 resistive_touch: resistive-touch { 1077 compatible = "resistive-adc-touch"; 1078 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, 1079 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, 1080 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; 1081 io-channel-names = "x", "y", "pressure"; 1082 touchscreen-min-pressure = <50000>; 1083 status = "disabled"; 1084 }; 1085 1086 pioA: pinctrl@fc038000 { 1087 compatible = "atmel,sama5d2-pinctrl"; 1088 reg = <0xfc038000 0x600>; 1089 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, 1090 <68 IRQ_TYPE_LEVEL_HIGH 7>, 1091 <69 IRQ_TYPE_LEVEL_HIGH 7>, 1092 <70 IRQ_TYPE_LEVEL_HIGH 7>; 1093 interrupt-controller; 1094 #interrupt-cells = <2>; 1095 gpio-controller; 1096 #gpio-cells = <2>; 1097 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1098 }; 1099 1100 pioBU: secumod@fc040000 { 1101 compatible = "atmel,sama5d2-secumod", "syscon"; 1102 reg = <0xfc040000 0x100>; 1103 1104 gpio-controller; 1105 #gpio-cells = <2>; 1106 status = "disabled"; 1107 secure-status = "okay"; 1108 }; 1109 1110 tdes@fc044000 { 1111 compatible = "atmel,at91sam9g46-tdes"; 1112 reg = <0xfc044000 0x100>; 1113 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 1114 dmas = <&dma0 1115 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1116 AT91_XDMAC_DT_PERID(28))>, 1117 <&dma0 1118 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1119 AT91_XDMAC_DT_PERID(29))>; 1120 dma-names = "tx", "rx"; 1121 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 1122 clock-names = "tdes_clk"; 1123 status = "okay"; 1124 }; 1125 1126 classd: classd@fc048000 { 1127 compatible = "atmel,sama5d2-classd"; 1128 reg = <0xfc048000 0x100>; 1129 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; 1130 dmas = <&dma0 1131 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1132 AT91_XDMAC_DT_PERID(47))>; 1133 dma-names = "tx"; 1134 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 1135 clock-names = "pclk", "gclk"; 1136 status = "disabled"; 1137 }; 1138 1139 i2s1: i2s@fc04c000 { 1140 compatible = "atmel,sama5d2-i2s"; 1141 reg = <0xfc04c000 0x100>; 1142 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; 1143 dmas = <&dma0 1144 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1145 AT91_XDMAC_DT_PERID(33))>, 1146 <&dma0 1147 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1148 AT91_XDMAC_DT_PERID(34))>; 1149 dma-names = "tx", "rx"; 1150 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; 1151 clock-names = "pclk", "gclk"; 1152 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; 1153 assigned-parrents = <&pmc PMC_TYPE_GCK 55>; 1154 status = "disabled"; 1155 }; 1156 1157 can1: can@fc050000 { 1158 compatible = "bosch,m_can"; 1159 reg = <0xfc050000 0x4000>, <0x210000 0x3800>; 1160 reg-names = "m_can", "message_ram"; 1161 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, 1162 <65 IRQ_TYPE_LEVEL_HIGH 7>; 1163 interrupt-names = "int0", "int1"; 1164 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 1165 clock-names = "hclk", "cclk"; 1166 assigned-clocks = <&pmc PMC_TYPE_GCK 57>; 1167 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 1168 assigned-clock-rates = <40000000>; 1169 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; 1170 status = "disabled"; 1171 }; 1172 1173 sfrbu: sfr@fc05c000 { 1174 compatible = "atmel,sama5d2-sfrbu", "syscon"; 1175 reg = <0xfc05c000 0x20>; 1176 }; 1177 1178 chipid@fc069000 { 1179 compatible = "atmel,sama5d2-chipid"; 1180 reg = <0xfc069000 0x8>; 1181 }; 1182 }; 1183 }; 1184}; 1185