1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree Include file for Layerscape-LX2160A family SoC. 4// 5// Copyright 2018-2020 NXP 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/memreserve/ 0x80000000 0x00010000; 11 12/ { 13 compatible = "fsl,lx2160a"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 rtc1 = &ftm_alarm0; 20 }; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 // 8 clusters having 2 Cortex-A72 cores each 27 cpu0: cpu@0 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a72"; 30 enable-method = "psci"; 31 reg = <0x0>; 32 clocks = <&clockgen 1 0>; 33 d-cache-size = <0x8000>; 34 d-cache-line-size = <64>; 35 d-cache-sets = <128>; 36 i-cache-size = <0xC000>; 37 i-cache-line-size = <64>; 38 i-cache-sets = <192>; 39 next-level-cache = <&cluster0_l2>; 40 cpu-idle-states = <&cpu_pw15>; 41 #cooling-cells = <2>; 42 }; 43 44 cpu1: cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a72"; 47 enable-method = "psci"; 48 reg = <0x1>; 49 clocks = <&clockgen 1 0>; 50 d-cache-size = <0x8000>; 51 d-cache-line-size = <64>; 52 d-cache-sets = <128>; 53 i-cache-size = <0xC000>; 54 i-cache-line-size = <64>; 55 i-cache-sets = <192>; 56 next-level-cache = <&cluster0_l2>; 57 cpu-idle-states = <&cpu_pw15>; 58 #cooling-cells = <2>; 59 }; 60 61 cpu100: cpu@100 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a72"; 64 enable-method = "psci"; 65 reg = <0x100>; 66 clocks = <&clockgen 1 1>; 67 d-cache-size = <0x8000>; 68 d-cache-line-size = <64>; 69 d-cache-sets = <128>; 70 i-cache-size = <0xC000>; 71 i-cache-line-size = <64>; 72 i-cache-sets = <192>; 73 next-level-cache = <&cluster1_l2>; 74 cpu-idle-states = <&cpu_pw15>; 75 #cooling-cells = <2>; 76 }; 77 78 cpu101: cpu@101 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a72"; 81 enable-method = "psci"; 82 reg = <0x101>; 83 clocks = <&clockgen 1 1>; 84 d-cache-size = <0x8000>; 85 d-cache-line-size = <64>; 86 d-cache-sets = <128>; 87 i-cache-size = <0xC000>; 88 i-cache-line-size = <64>; 89 i-cache-sets = <192>; 90 next-level-cache = <&cluster1_l2>; 91 cpu-idle-states = <&cpu_pw15>; 92 #cooling-cells = <2>; 93 }; 94 95 cpu200: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a72"; 98 enable-method = "psci"; 99 reg = <0x200>; 100 clocks = <&clockgen 1 2>; 101 d-cache-size = <0x8000>; 102 d-cache-line-size = <64>; 103 d-cache-sets = <128>; 104 i-cache-size = <0xC000>; 105 i-cache-line-size = <64>; 106 i-cache-sets = <192>; 107 next-level-cache = <&cluster2_l2>; 108 cpu-idle-states = <&cpu_pw15>; 109 #cooling-cells = <2>; 110 }; 111 112 cpu201: cpu@201 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a72"; 115 enable-method = "psci"; 116 reg = <0x201>; 117 clocks = <&clockgen 1 2>; 118 d-cache-size = <0x8000>; 119 d-cache-line-size = <64>; 120 d-cache-sets = <128>; 121 i-cache-size = <0xC000>; 122 i-cache-line-size = <64>; 123 i-cache-sets = <192>; 124 next-level-cache = <&cluster2_l2>; 125 cpu-idle-states = <&cpu_pw15>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu300: cpu@300 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a72"; 132 enable-method = "psci"; 133 reg = <0x300>; 134 clocks = <&clockgen 1 3>; 135 d-cache-size = <0x8000>; 136 d-cache-line-size = <64>; 137 d-cache-sets = <128>; 138 i-cache-size = <0xC000>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <192>; 141 next-level-cache = <&cluster3_l2>; 142 cpu-idle-states = <&cpu_pw15>; 143 #cooling-cells = <2>; 144 }; 145 146 cpu301: cpu@301 { 147 device_type = "cpu"; 148 compatible = "arm,cortex-a72"; 149 enable-method = "psci"; 150 reg = <0x301>; 151 clocks = <&clockgen 1 3>; 152 d-cache-size = <0x8000>; 153 d-cache-line-size = <64>; 154 d-cache-sets = <128>; 155 i-cache-size = <0xC000>; 156 i-cache-line-size = <64>; 157 i-cache-sets = <192>; 158 next-level-cache = <&cluster3_l2>; 159 cpu-idle-states = <&cpu_pw15>; 160 #cooling-cells = <2>; 161 }; 162 163 cpu400: cpu@400 { 164 device_type = "cpu"; 165 compatible = "arm,cortex-a72"; 166 enable-method = "psci"; 167 reg = <0x400>; 168 clocks = <&clockgen 1 4>; 169 d-cache-size = <0x8000>; 170 d-cache-line-size = <64>; 171 d-cache-sets = <128>; 172 i-cache-size = <0xC000>; 173 i-cache-line-size = <64>; 174 i-cache-sets = <192>; 175 next-level-cache = <&cluster4_l2>; 176 cpu-idle-states = <&cpu_pw15>; 177 #cooling-cells = <2>; 178 }; 179 180 cpu401: cpu@401 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a72"; 183 enable-method = "psci"; 184 reg = <0x401>; 185 clocks = <&clockgen 1 4>; 186 d-cache-size = <0x8000>; 187 d-cache-line-size = <64>; 188 d-cache-sets = <128>; 189 i-cache-size = <0xC000>; 190 i-cache-line-size = <64>; 191 i-cache-sets = <192>; 192 next-level-cache = <&cluster4_l2>; 193 cpu-idle-states = <&cpu_pw15>; 194 #cooling-cells = <2>; 195 }; 196 197 cpu500: cpu@500 { 198 device_type = "cpu"; 199 compatible = "arm,cortex-a72"; 200 enable-method = "psci"; 201 reg = <0x500>; 202 clocks = <&clockgen 1 5>; 203 d-cache-size = <0x8000>; 204 d-cache-line-size = <64>; 205 d-cache-sets = <128>; 206 i-cache-size = <0xC000>; 207 i-cache-line-size = <64>; 208 i-cache-sets = <192>; 209 next-level-cache = <&cluster5_l2>; 210 cpu-idle-states = <&cpu_pw15>; 211 #cooling-cells = <2>; 212 }; 213 214 cpu501: cpu@501 { 215 device_type = "cpu"; 216 compatible = "arm,cortex-a72"; 217 enable-method = "psci"; 218 reg = <0x501>; 219 clocks = <&clockgen 1 5>; 220 d-cache-size = <0x8000>; 221 d-cache-line-size = <64>; 222 d-cache-sets = <128>; 223 i-cache-size = <0xC000>; 224 i-cache-line-size = <64>; 225 i-cache-sets = <192>; 226 next-level-cache = <&cluster5_l2>; 227 cpu-idle-states = <&cpu_pw15>; 228 #cooling-cells = <2>; 229 }; 230 231 cpu600: cpu@600 { 232 device_type = "cpu"; 233 compatible = "arm,cortex-a72"; 234 enable-method = "psci"; 235 reg = <0x600>; 236 clocks = <&clockgen 1 6>; 237 d-cache-size = <0x8000>; 238 d-cache-line-size = <64>; 239 d-cache-sets = <128>; 240 i-cache-size = <0xC000>; 241 i-cache-line-size = <64>; 242 i-cache-sets = <192>; 243 next-level-cache = <&cluster6_l2>; 244 cpu-idle-states = <&cpu_pw15>; 245 #cooling-cells = <2>; 246 }; 247 248 cpu601: cpu@601 { 249 device_type = "cpu"; 250 compatible = "arm,cortex-a72"; 251 enable-method = "psci"; 252 reg = <0x601>; 253 clocks = <&clockgen 1 6>; 254 d-cache-size = <0x8000>; 255 d-cache-line-size = <64>; 256 d-cache-sets = <128>; 257 i-cache-size = <0xC000>; 258 i-cache-line-size = <64>; 259 i-cache-sets = <192>; 260 next-level-cache = <&cluster6_l2>; 261 cpu-idle-states = <&cpu_pw15>; 262 #cooling-cells = <2>; 263 }; 264 265 cpu700: cpu@700 { 266 device_type = "cpu"; 267 compatible = "arm,cortex-a72"; 268 enable-method = "psci"; 269 reg = <0x700>; 270 clocks = <&clockgen 1 7>; 271 d-cache-size = <0x8000>; 272 d-cache-line-size = <64>; 273 d-cache-sets = <128>; 274 i-cache-size = <0xC000>; 275 i-cache-line-size = <64>; 276 i-cache-sets = <192>; 277 next-level-cache = <&cluster7_l2>; 278 cpu-idle-states = <&cpu_pw15>; 279 #cooling-cells = <2>; 280 }; 281 282 cpu701: cpu@701 { 283 device_type = "cpu"; 284 compatible = "arm,cortex-a72"; 285 enable-method = "psci"; 286 reg = <0x701>; 287 clocks = <&clockgen 1 7>; 288 d-cache-size = <0x8000>; 289 d-cache-line-size = <64>; 290 d-cache-sets = <128>; 291 i-cache-size = <0xC000>; 292 i-cache-line-size = <64>; 293 i-cache-sets = <192>; 294 next-level-cache = <&cluster7_l2>; 295 cpu-idle-states = <&cpu_pw15>; 296 #cooling-cells = <2>; 297 }; 298 299 cluster0_l2: l2-cache0 { 300 compatible = "cache"; 301 cache-size = <0x100000>; 302 cache-line-size = <64>; 303 cache-sets = <1024>; 304 cache-level = <2>; 305 }; 306 307 cluster1_l2: l2-cache1 { 308 compatible = "cache"; 309 cache-size = <0x100000>; 310 cache-line-size = <64>; 311 cache-sets = <1024>; 312 cache-level = <2>; 313 }; 314 315 cluster2_l2: l2-cache2 { 316 compatible = "cache"; 317 cache-size = <0x100000>; 318 cache-line-size = <64>; 319 cache-sets = <1024>; 320 cache-level = <2>; 321 }; 322 323 cluster3_l2: l2-cache3 { 324 compatible = "cache"; 325 cache-size = <0x100000>; 326 cache-line-size = <64>; 327 cache-sets = <1024>; 328 cache-level = <2>; 329 }; 330 331 cluster4_l2: l2-cache4 { 332 compatible = "cache"; 333 cache-size = <0x100000>; 334 cache-line-size = <64>; 335 cache-sets = <1024>; 336 cache-level = <2>; 337 }; 338 339 cluster5_l2: l2-cache5 { 340 compatible = "cache"; 341 cache-size = <0x100000>; 342 cache-line-size = <64>; 343 cache-sets = <1024>; 344 cache-level = <2>; 345 }; 346 347 cluster6_l2: l2-cache6 { 348 compatible = "cache"; 349 cache-size = <0x100000>; 350 cache-line-size = <64>; 351 cache-sets = <1024>; 352 cache-level = <2>; 353 }; 354 355 cluster7_l2: l2-cache7 { 356 compatible = "cache"; 357 cache-size = <0x100000>; 358 cache-line-size = <64>; 359 cache-sets = <1024>; 360 cache-level = <2>; 361 }; 362 363 cpu_pw15: cpu-pw15 { 364 compatible = "arm,idle-state"; 365 idle-state-name = "PW15"; 366 arm,psci-suspend-param = <0x0>; 367 entry-latency-us = <2000>; 368 exit-latency-us = <2000>; 369 min-residency-us = <6000>; 370 }; 371 }; 372 373 gic: interrupt-controller@6000000 { 374 compatible = "arm,gic-v3"; 375 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 376 <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 377 // SGI_base) 378 <0x0 0x0c0c0000 0 0x2000>, // GICC 379 <0x0 0x0c0d0000 0 0x1000>, // GICH 380 <0x0 0x0c0e0000 0 0x20000>; // GICV 381 #interrupt-cells = <3>; 382 #address-cells = <2>; 383 #size-cells = <2>; 384 ranges; 385 interrupt-controller; 386 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 387 388 its: gic-its@6020000 { 389 compatible = "arm,gic-v3-its"; 390 msi-controller; 391 reg = <0x0 0x6020000 0 0x20000>; 392 }; 393 }; 394 395 timer { 396 compatible = "arm,armv8-timer"; 397 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 401 }; 402 403 pmu { 404 compatible = "arm,cortex-a72-pmu"; 405 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 406 }; 407 408 psci { 409 compatible = "arm,psci-0.2"; 410 method = "smc"; 411 }; 412 413 memory@80000000 { 414 // DRAM space - 1, size : 2 GB DRAM 415 device_type = "memory"; 416 reg = <0x00000000 0x80000000 0 0x80000000>; 417 }; 418 419 memory@2080000000 { 420 // DRAM space - 1, size : 126 GB DRAM 421 device_type = "memory"; 422 reg = <0x00000020 0x80000000 0x0000001F 0x80000000>; 423 }; 424 425 ddr1: memory-controller@1080000 { 426 compatible = "fsl,qoriq-memory-controller"; 427 reg = <0x0 0x1080000 0x0 0x1000>; 428 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 429 little-endian; 430 }; 431 432 ddr2: memory-controller@1090000 { 433 compatible = "fsl,qoriq-memory-controller"; 434 reg = <0x0 0x1090000 0x0 0x1000>; 435 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 436 little-endian; 437 }; 438 439 // One clock unit-sysclk node which bootloader require during DT fix-up 440 sysclk: sysclk { 441 compatible = "fixed-clock"; 442 #clock-cells = <0>; 443 clock-frequency = <100000000>; // fixed up by bootloader 444 clock-output-names = "sysclk"; 445 }; 446 447 thermal-zones { 448 core_thermal1: core-thermal1 { 449 polling-delay-passive = <1000>; 450 polling-delay = <5000>; 451 thermal-sensors = <&tmu 0>; 452 453 trips { 454 core_cluster_alert: core-cluster-alert { 455 temperature = <85000>; 456 hysteresis = <2000>; 457 type = "passive"; 458 }; 459 460 core_cluster_crit: core-cluster-crit { 461 temperature = <95000>; 462 hysteresis = <2000>; 463 type = "critical"; 464 }; 465 }; 466 467 }; 468 }; 469 470 soc { 471 compatible = "simple-bus"; 472 #address-cells = <2>; 473 #size-cells = <2>; 474 ranges; 475 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 476 477 crypto: crypto@8000000 { 478 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 479 fsl,sec-era = <10>; 480 #address-cells = <1>; 481 #size-cells = <1>; 482 ranges = <0x0 0x00 0x8000000 0x100000>; 483 reg = <0x00 0x8000000 0x0 0x100000>; 484 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 485 dma-coherent; 486 status = "disabled"; 487 488 sec_jr0: jr@10000 { 489 compatible = "fsl,sec-v5.0-job-ring", 490 "fsl,sec-v4.0-job-ring"; 491 reg = <0x10000 0x10000>; 492 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 493 status = "okay"; secure-status = "disabled"; /* NS-only */ 494 }; 495 496 sec_jr1: jr@20000 { 497 compatible = "fsl,sec-v5.0-job-ring", 498 "fsl,sec-v4.0-job-ring"; 499 reg = <0x20000 0x10000>; 500 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 501 status = "okay"; secure-status = "disabled"; /* NS-only */ 502 }; 503 504 sec_jr2: jr@30000 { 505 compatible = "fsl,sec-v5.0-job-ring", 506 "fsl,sec-v4.0-job-ring"; 507 reg = <0x30000 0x10000>; 508 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 509 status = "disabled"; secure-status = "okay"; /* S-only */ 510 }; 511 512 sec_jr3: jr@40000 { 513 compatible = "fsl,sec-v5.0-job-ring", 514 "fsl,sec-v4.0-job-ring"; 515 reg = <0x40000 0x10000>; 516 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 517 status = "okay"; secure-status = "disabled"; /* workaround for ATF */ 518 }; 519 }; 520 521 clockgen: clock-controller@1300000 { 522 compatible = "fsl,lx2160a-clockgen"; 523 reg = <0 0x1300000 0 0xa0000>; 524 #clock-cells = <2>; 525 clocks = <&sysclk>; 526 }; 527 528 dcfg: syscon@1e00000 { 529 compatible = "fsl,lx2160a-dcfg", "syscon"; 530 reg = <0x0 0x1e00000 0x0 0x10000>; 531 little-endian; 532 }; 533 534 sfp: sfp@1e80000 { 535 compatible = "fsl,lx2160a-sfp"; 536 reg = <0x0 0x1e80000 0x0 0x1000>; 537 }; 538 539 sec_mon: sec-mon@1e90000 { 540 compatible = "fsl,lx2160a-sec-mon"; 541 reg = <0x0 0x1e90000 0x0 0x1000>; 542 status = "disabled"; 543 secure-status = "okay"; 544 }; 545 546 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 547 emdio1: mdio@8b96000 { 548 compatible = "fsl,fman-memac-mdio"; 549 reg = <0x0 0x8b96000 0x0 0x1000>; 550 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 little-endian; /* force the driver in LE mode */ 554 status = "disabled"; 555 }; 556 557 /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */ 558 emdio2: mdio@8b97000 { 559 compatible = "fsl,fman-memac-mdio"; 560 reg = <0x0 0x8b97000 0x0 0x1000>; 561 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 little-endian; /* force the driver in LE mode */ 565 status = "disabled"; 566 }; 567 568 i2c0: i2c@2000000 { 569 compatible = "fsl,vf610-i2c"; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 reg = <0x0 0x2000000 0x0 0x10000>; 573 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 574 clock-names = "i2c"; 575 clocks = <&clockgen 4 15>; 576 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 577 status = "disabled"; 578 }; 579 580 i2c1: i2c@2010000 { 581 compatible = "fsl,vf610-i2c"; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 reg = <0x0 0x2010000 0x0 0x10000>; 585 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 586 clock-names = "i2c"; 587 clocks = <&clockgen 4 15>; 588 status = "disabled"; 589 }; 590 591 i2c2: i2c@2020000 { 592 compatible = "fsl,vf610-i2c"; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 reg = <0x0 0x2020000 0x0 0x10000>; 596 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 597 clock-names = "i2c"; 598 clocks = <&clockgen 4 15>; 599 status = "disabled"; 600 }; 601 602 i2c3: i2c@2030000 { 603 compatible = "fsl,vf610-i2c"; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 reg = <0x0 0x2030000 0x0 0x10000>; 607 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 608 clock-names = "i2c"; 609 clocks = <&clockgen 4 15>; 610 status = "disabled"; 611 }; 612 613 i2c4: i2c@2040000 { 614 compatible = "fsl,vf610-i2c"; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 reg = <0x0 0x2040000 0x0 0x10000>; 618 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 619 clock-names = "i2c"; 620 clocks = <&clockgen 4 15>; 621 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 622 status = "disabled"; 623 }; 624 625 i2c5: i2c@2050000 { 626 compatible = "fsl,vf610-i2c"; 627 #address-cells = <1>; 628 #size-cells = <0>; 629 reg = <0x0 0x2050000 0x0 0x10000>; 630 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 631 clock-names = "i2c"; 632 clocks = <&clockgen 4 15>; 633 status = "disabled"; 634 }; 635 636 i2c6: i2c@2060000 { 637 compatible = "fsl,vf610-i2c"; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 reg = <0x0 0x2060000 0x0 0x10000>; 641 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 642 clock-names = "i2c"; 643 clocks = <&clockgen 4 15>; 644 status = "disabled"; 645 }; 646 647 i2c7: i2c@2070000 { 648 compatible = "fsl,vf610-i2c"; 649 #address-cells = <1>; 650 #size-cells = <0>; 651 reg = <0x0 0x2070000 0x0 0x10000>; 652 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 653 clock-names = "i2c"; 654 clocks = <&clockgen 4 15>; 655 status = "disabled"; 656 }; 657 658 fspi: spi@20c0000 { 659 compatible = "nxp,lx2160a-fspi"; 660 #address-cells = <1>; 661 #size-cells = <0>; 662 reg = <0x0 0x20c0000 0x0 0x10000>, 663 <0x0 0x20000000 0x0 0x10000000>; 664 reg-names = "fspi_base", "fspi_mmap"; 665 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 667 clock-names = "fspi_en", "fspi"; 668 status = "disabled"; 669 }; 670 671 dspi0: spi@2100000 { 672 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 reg = <0x0 0x2100000 0x0 0x10000>; 676 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&clockgen 4 7>; 678 clock-names = "dspi"; 679 spi-num-chipselects = <5>; 680 bus-num = <0>; 681 status = "disabled"; 682 }; 683 684 dspi1: spi@2110000 { 685 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 reg = <0x0 0x2110000 0x0 0x10000>; 689 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&clockgen 4 7>; 691 clock-names = "dspi"; 692 spi-num-chipselects = <5>; 693 bus-num = <1>; 694 status = "disabled"; 695 }; 696 697 dspi2: spi@2120000 { 698 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 reg = <0x0 0x2120000 0x0 0x10000>; 702 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&clockgen 4 7>; 704 clock-names = "dspi"; 705 spi-num-chipselects = <5>; 706 bus-num = <2>; 707 status = "disabled"; 708 }; 709 710 esdhc0: esdhc@2140000 { 711 compatible = "fsl,esdhc"; 712 reg = <0x0 0x2140000 0x0 0x10000>; 713 interrupts = <0 28 0x4>; /* Level high type */ 714 clocks = <&clockgen 4 1>; 715 voltage-ranges = <1800 1800 3300 3300>; 716 sdhci,auto-cmd12; 717 little-endian; 718 bus-width = <4>; 719 status = "disabled"; 720 }; 721 722 esdhc1: esdhc@2150000 { 723 compatible = "fsl,esdhc"; 724 reg = <0x0 0x2150000 0x0 0x10000>; 725 interrupts = <0 63 0x4>; /* Level high type */ 726 clocks = <&clockgen 4 1>; 727 voltage-ranges = <1800 1800 3300 3300>; 728 sdhci,auto-cmd12; 729 broken-cd; 730 little-endian; 731 bus-width = <4>; 732 status = "disabled"; 733 }; 734 735 can0: can@2180000 { 736 compatible = "fsl,lx2160ar1-flexcan"; 737 reg = <0x0 0x2180000 0x0 0x10000>; 738 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&sysclk>, <&clockgen 4 7>; 740 clock-names = "ipg", "per"; 741 status = "disabled"; 742 }; 743 744 can1: can@2190000 { 745 compatible = "fsl,lx2160ar1-flexcan"; 746 reg = <0x0 0x2190000 0x0 0x10000>; 747 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&sysclk>, <&clockgen 4 7>; 749 clock-names = "ipg", "per"; 750 status = "disabled"; 751 }; 752 753 tmu: tmu@1f80000 { 754 compatible = "fsl,qoriq-tmu"; 755 reg = <0x0 0x1f80000 0x0 0x10000>; 756 interrupts = <0 23 0x4>; 757 fsl,tmu-range = <0x800000E6 0x8001017D>; 758 fsl,tmu-calibration = 759 /* Calibration data group 1 */ 760 <0x00000000 0x00000035 761 /* Calibration data group 2 */ 762 0x00010001 0x00000154>; 763 little-endian; 764 #thermal-sensor-cells = <1>; 765 }; 766 767 uart0: serial@21c0000 { 768 compatible = "arm,sbsa-uart","arm,pl011"; 769 reg = <0x0 0x21c0000 0x0 0x1000>; 770 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 771 current-speed = <115200>; 772 status = "disabled"; 773 }; 774 775 uart1: serial@21d0000 { 776 compatible = "arm,sbsa-uart","arm,pl011"; 777 reg = <0x0 0x21d0000 0x0 0x1000>; 778 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 779 current-speed = <115200>; 780 status = "disabled"; 781 }; 782 783 uart2: serial@21e0000 { 784 compatible = "arm,sbsa-uart","arm,pl011"; 785 reg = <0x0 0x21e0000 0x0 0x1000>; 786 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 787 current-speed = <115200>; 788 status = "disabled"; 789 }; 790 791 uart3: serial@21f0000 { 792 compatible = "arm,sbsa-uart","arm,pl011"; 793 reg = <0x0 0x21f0000 0x0 0x1000>; 794 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 795 current-speed = <115200>; 796 status = "disabled"; 797 }; 798 799 gpio0: gpio@2300000 { 800 compatible = "fsl,qoriq-gpio"; 801 reg = <0x0 0x2300000 0x0 0x10000>; 802 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 803 gpio-controller; 804 little-endian; 805 #gpio-cells = <2>; 806 interrupt-controller; 807 #interrupt-cells = <2>; 808 }; 809 810 gpio1: gpio@2310000 { 811 compatible = "fsl,qoriq-gpio"; 812 reg = <0x0 0x2310000 0x0 0x10000>; 813 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 814 gpio-controller; 815 little-endian; 816 #gpio-cells = <2>; 817 interrupt-controller; 818 #interrupt-cells = <2>; 819 }; 820 821 gpio2: gpio@2320000 { 822 compatible = "fsl,qoriq-gpio"; 823 reg = <0x0 0x2320000 0x0 0x10000>; 824 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 825 gpio-controller; 826 little-endian; 827 #gpio-cells = <2>; 828 interrupt-controller; 829 #interrupt-cells = <2>; 830 }; 831 832 gpio3: gpio@2330000 { 833 compatible = "fsl,qoriq-gpio"; 834 reg = <0x0 0x2330000 0x0 0x10000>; 835 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 836 gpio-controller; 837 little-endian; 838 #gpio-cells = <2>; 839 interrupt-controller; 840 #interrupt-cells = <2>; 841 }; 842 843 watchdog@23a0000 { 844 compatible = "arm,sbsa-gwdt"; 845 reg = <0x0 0x23a0000 0 0x1000>, 846 <0x0 0x2390000 0 0x1000>; 847 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 848 timeout-sec = <30>; 849 }; 850 851 rcpm: rcpm@1e34040 { 852 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; 853 reg = <0x0 0x1e34040 0x0 0x1c>; 854 #fsl,rcpm-wakeup-cells = <7>; 855 little-endian; 856 }; 857 858 ftm_alarm0: timer@2800000 { 859 compatible = "fsl,lx2160a-ftm-alarm"; 860 reg = <0x0 0x2800000 0x0 0x10000>; 861 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 862 interrupts = <0 44 4>; 863 }; 864 865 usb0: usb@3100000 { 866 compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; 867 reg = <0x0 0x3100000 0x0 0x10000>; 868 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 869 dr_mode = "host"; 870 snps,quirk-frame-length-adjustment = <0x20>; 871 usb3-lpm-capable; 872 snps,dis-u1u2-when-u3-quirk; 873 snps,dis_rxdet_inp3_quirk; 874 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 875 snps,host-vbus-glitches; 876 dma-coherent; 877 status = "disabled"; 878 }; 879 880 usb1: usb@3110000 { 881 compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; 882 reg = <0x0 0x3110000 0x0 0x10000>; 883 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 884 dr_mode = "host"; 885 snps,quirk-frame-length-adjustment = <0x20>; 886 usb3-lpm-capable; 887 snps,dis-u1u2-when-u3-quirk; 888 snps,dis_rxdet_inp3_quirk; 889 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 890 snps,host-vbus-glitches; 891 status = "disabled"; 892 }; 893 894 sata0: sata@3200000 { 895 compatible = "fsl,lx2160a-ahci"; 896 reg = <0x0 0x3200000 0x0 0x10000>, 897 <0x7 0x100520 0x0 0x4>; 898 reg-names = "ahci", "sata-ecc"; 899 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&clockgen 4 3>; 901 dma-coherent; 902 status = "disabled"; 903 }; 904 905 sata1: sata@3210000 { 906 compatible = "fsl,lx2160a-ahci"; 907 reg = <0x0 0x3210000 0x0 0x10000>, 908 <0x7 0x100520 0x0 0x4>; 909 reg-names = "ahci", "sata-ecc"; 910 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&clockgen 4 3>; 912 dma-coherent; 913 status = "disabled"; 914 }; 915 916 sata2: sata@3220000 { 917 compatible = "fsl,lx2160a-ahci"; 918 reg = <0x0 0x3220000 0x0 0x10000>, 919 <0x7 0x100520 0x0 0x4>; 920 reg-names = "ahci", "sata-ecc"; 921 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&clockgen 4 3>; 923 dma-coherent; 924 status = "disabled"; 925 }; 926 927 sata3: sata@3230000 { 928 compatible = "fsl,lx2160a-ahci"; 929 reg = <0x0 0x3230000 0x0 0x10000>, 930 <0x7 0x100520 0x0 0x4>; 931 reg-names = "ahci", "sata-ecc"; 932 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&clockgen 4 3>; 934 dma-coherent; 935 status = "disabled"; 936 }; 937 938 pcie@3400000 { 939 compatible = "fsl,lx2160a-pcie"; 940 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 941 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ 942 reg-names = "csr_axi_slave", "config_axi_slave"; 943 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 944 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 945 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 946 interrupt-names = "aer", "pme", "intr"; 947 #address-cells = <3>; 948 #size-cells = <2>; 949 device_type = "pci"; 950 dma-coherent; 951 apio-wins = <8>; 952 ppio-wins = <8>; 953 bus-range = <0x0 0xff>; 954 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 955 msi-parent = <&its>; 956 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 957 #interrupt-cells = <1>; 958 interrupt-map-mask = <0 0 0 7>; 959 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 960 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 961 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 962 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 963 status = "disabled"; 964 }; 965 966 pcie_ep@3400000 { 967 compatible = "fsl,lx2160a-pcie-ep"; 968 reg = <0x00 0x03400000 0x0 0x00100000 969 0x80 0x00000000 0x8 0x00000000>; 970 reg-names = "regs", "addr_space"; 971 num-ob-windows = <256>; 972 status = "disabled"; 973 }; 974 975 pcie@3500000 { 976 compatible = "fsl,lx2160a-pcie"; 977 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 978 0x88 0x00000000 0x0 0x00001000>; /* configuration space */ 979 reg-names = "csr_axi_slave", "config_axi_slave"; 980 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 981 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 982 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 983 interrupt-names = "aer", "pme", "intr"; 984 #address-cells = <3>; 985 #size-cells = <2>; 986 device_type = "pci"; 987 dma-coherent; 988 apio-wins = <8>; 989 ppio-wins = <8>; 990 bus-range = <0x0 0xff>; 991 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 992 msi-parent = <&its>; 993 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 994 #interrupt-cells = <1>; 995 interrupt-map-mask = <0 0 0 7>; 996 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 997 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 998 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 999 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1000 status = "disabled"; 1001 }; 1002 1003 pcie_ep@3500000 { 1004 compatible = "fsl,lx2160a-pcie-ep"; 1005 reg = <0x00 0x03500000 0x0 0x00100000 1006 0x88 0x00000000 0x8 0x00000000>; 1007 reg-names = "regs", "addr_space"; 1008 num-ob-windows = <256>; 1009 status = "disabled"; 1010 }; 1011 1012 pcie@3600000 { 1013 compatible = "fsl,lx2160a-pcie"; 1014 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 1015 0x90 0x00000000 0x0 0x00001000>; /* configuration space */ 1016 reg-names = "csr_axi_slave", "config_axi_slave"; 1017 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1018 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1019 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1020 interrupt-names = "aer", "pme", "intr"; 1021 #address-cells = <3>; 1022 #size-cells = <2>; 1023 device_type = "pci"; 1024 dma-coherent; 1025 apio-wins = <8>; 1026 ppio-wins = <8>; 1027 bus-range = <0x0 0xff>; 1028 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1029 msi-parent = <&its>; 1030 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1031 #interrupt-cells = <1>; 1032 interrupt-map-mask = <0 0 0 7>; 1033 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1034 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1035 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1036 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1037 status = "disabled"; 1038 }; 1039 1040 pcie_ep@3600000 { 1041 compatible = "fsl,lx2160a-pcie-ep"; 1042 reg = <0x00 0x03600000 0x0 0x00100000 1043 0x90 0x00000000 0x8 0x00000000>; 1044 reg-names = "regs", "addr_space"; 1045 num-ob-windows = <256>; 1046 max-functions = <2>; 1047 status = "disabled"; 1048 }; 1049 1050 pcie@3700000 { 1051 compatible = "fsl,lx2160a-pcie"; 1052 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 1053 0x98 0x00000000 0x0 0x00001000>; /* configuration space */ 1054 reg-names = "csr_axi_slave", "config_axi_slave"; 1055 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1056 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1057 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1058 interrupt-names = "aer", "pme", "intr"; 1059 #address-cells = <3>; 1060 #size-cells = <2>; 1061 device_type = "pci"; 1062 dma-coherent; 1063 apio-wins = <8>; 1064 ppio-wins = <8>; 1065 bus-range = <0x0 0xff>; 1066 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1067 msi-parent = <&its>; 1068 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1069 #interrupt-cells = <1>; 1070 interrupt-map-mask = <0 0 0 7>; 1071 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1072 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1073 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1074 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1075 status = "disabled"; 1076 }; 1077 1078 pcie_ep@3700000 { 1079 compatible = "fsl,lx2160a-pcie-ep"; 1080 reg = <0x00 0x03700000 0x0 0x00100000 1081 0x98 0x00000000 0x8 0x00000000>; 1082 reg-names = "regs", "addr_space"; 1083 num-ob-windows = <256>; 1084 status = "disabled"; 1085 }; 1086 1087 pcie@3800000 { 1088 compatible = "fsl,lx2160a-pcie"; 1089 reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ 1090 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */ 1091 reg-names = "csr_axi_slave", "config_axi_slave"; 1092 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1093 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1094 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1095 interrupt-names = "aer", "pme", "intr"; 1096 #address-cells = <3>; 1097 #size-cells = <2>; 1098 device_type = "pci"; 1099 dma-coherent; 1100 apio-wins = <8>; 1101 ppio-wins = <8>; 1102 bus-range = <0x0 0xff>; 1103 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1104 msi-parent = <&its>; 1105 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1106 #interrupt-cells = <1>; 1107 interrupt-map-mask = <0 0 0 7>; 1108 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1109 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1110 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1111 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1112 status = "disabled"; 1113 }; 1114 1115 pcie_ep@3800000 { 1116 compatible = "fsl,lx2160a-pcie-ep"; 1117 reg = <0x00 0x03800000 0x0 0x00100000 1118 0xa0 0x00000000 0x8 0x00000000>; 1119 reg-names = "regs", "addr_space"; 1120 num-ob-windows = <256>; 1121 max-functions = <2>; 1122 status = "disabled"; 1123 }; 1124 1125 pcie@3900000 { 1126 compatible = "fsl,lx2160a-pcie"; 1127 reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ 1128 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */ 1129 reg-names = "csr_axi_slave", "config_axi_slave"; 1130 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1131 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1132 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1133 interrupt-names = "aer", "pme", "intr"; 1134 #address-cells = <3>; 1135 #size-cells = <2>; 1136 device_type = "pci"; 1137 dma-coherent; 1138 apio-wins = <8>; 1139 ppio-wins = <8>; 1140 bus-range = <0x0 0xff>; 1141 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1142 msi-parent = <&its>; 1143 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1144 #interrupt-cells = <1>; 1145 interrupt-map-mask = <0 0 0 7>; 1146 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1147 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1148 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1149 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1150 status = "disabled"; 1151 }; 1152 1153 pcie_ep@3900000 { 1154 compatible = "fsl,lx2160a-pcie-ep"; 1155 reg = <0x00 0x03900000 0x0 0x00100000 1156 0xa8 0x00000000 0x8 0x00000000>; 1157 reg-names = "regs", "addr_space"; 1158 num-ob-windows = <256>; 1159 status = "disabled"; 1160 }; 1161 1162 smmu: iommu@5000000 { 1163 compatible = "arm,mmu-500"; 1164 reg = <0 0x5000000 0 0x800000>; 1165 #iommu-cells = <1>; 1166 #global-interrupts = <14>; 1167 // global secure fault 1168 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1169 // combined secure 1170 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1171 // global non-secure fault 1172 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1173 // combined non-secure 1174 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1175 // performance counter interrupts 0-9 1176 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1186 // per context interrupt, 64 interrupts 1187 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1251 dma-coherent; 1252 }; 1253 1254 console@8340020 { 1255 compatible = "fsl,dpaa2-console"; 1256 reg = <0x00000000 0x08340020 0 0x2>; 1257 }; 1258 1259 ptp-timer@8b95000 { 1260 compatible = "fsl,dpaa2-ptp"; 1261 reg = <0x0 0x8b95000 0x0 0x100>; 1262 clocks = <&clockgen 4 1>; 1263 little-endian; 1264 fsl,extts-fifo; 1265 }; 1266 1267 fsl_mc: fsl-mc@80c000000 { 1268 compatible = "fsl,qoriq-mc"; 1269 reg = <0x00000008 0x0c000000 0 0x40>, 1270 <0x00000000 0x08340000 0 0x40000>; 1271 msi-parent = <&its>; 1272 /* iommu-map property is fixed up by u-boot */ 1273 iommu-map = <0 &smmu 0 0>; 1274 dma-coherent; 1275 #address-cells = <3>; 1276 #size-cells = <1>; 1277 1278 /* 1279 * Region type 0x0 - MC portals 1280 * Region type 0x1 - QBMAN portals 1281 */ 1282 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 1283 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 1284 1285 /* 1286 * Define the maximum number of MACs present on the SoC. 1287 */ 1288 dpmacs { 1289 #address-cells = <1>; 1290 #size-cells = <0>; 1291 1292 dpmac1: dpmac@1 { 1293 compatible = "fsl,qoriq-mc-dpmac"; 1294 reg = <0x1>; 1295 }; 1296 1297 dpmac2: dpmac@2 { 1298 compatible = "fsl,qoriq-mc-dpmac"; 1299 reg = <0x2>; 1300 }; 1301 1302 dpmac3: dpmac@3 { 1303 compatible = "fsl,qoriq-mc-dpmac"; 1304 reg = <0x3>; 1305 }; 1306 1307 dpmac4: dpmac@4 { 1308 compatible = "fsl,qoriq-mc-dpmac"; 1309 reg = <0x4>; 1310 }; 1311 1312 dpmac5: dpmac@5 { 1313 compatible = "fsl,qoriq-mc-dpmac"; 1314 reg = <0x5>; 1315 }; 1316 1317 dpmac6: dpmac@6 { 1318 compatible = "fsl,qoriq-mc-dpmac"; 1319 reg = <0x6>; 1320 }; 1321 1322 dpmac7: dpmac@7 { 1323 compatible = "fsl,qoriq-mc-dpmac"; 1324 reg = <0x7>; 1325 }; 1326 1327 dpmac8: dpmac@8 { 1328 compatible = "fsl,qoriq-mc-dpmac"; 1329 reg = <0x8>; 1330 }; 1331 1332 dpmac9: dpmac@9 { 1333 compatible = "fsl,qoriq-mc-dpmac"; 1334 reg = <0x9>; 1335 }; 1336 1337 dpmac10: dpmac@a { 1338 compatible = "fsl,qoriq-mc-dpmac"; 1339 reg = <0xa>; 1340 }; 1341 1342 dpmac11: dpmac@b { 1343 compatible = "fsl,qoriq-mc-dpmac"; 1344 reg = <0xb>; 1345 }; 1346 1347 dpmac12: dpmac@c { 1348 compatible = "fsl,qoriq-mc-dpmac"; 1349 reg = <0xc>; 1350 }; 1351 1352 dpmac13: dpmac@d { 1353 compatible = "fsl,qoriq-mc-dpmac"; 1354 reg = <0xd>; 1355 }; 1356 1357 dpmac14: dpmac@e { 1358 compatible = "fsl,qoriq-mc-dpmac"; 1359 reg = <0xe>; 1360 }; 1361 1362 dpmac15: dpmac@f { 1363 compatible = "fsl,qoriq-mc-dpmac"; 1364 reg = <0xf>; 1365 }; 1366 1367 dpmac16: dpmac@10 { 1368 compatible = "fsl,qoriq-mc-dpmac"; 1369 reg = <0x10>; 1370 }; 1371 1372 dpmac17: dpmac@11 { 1373 compatible = "fsl,qoriq-mc-dpmac"; 1374 reg = <0x11>; 1375 }; 1376 1377 dpmac18: dpmac@12 { 1378 compatible = "fsl,qoriq-mc-dpmac"; 1379 reg = <0x12>; 1380 }; 1381 }; 1382 }; 1383 }; 1384 1385 firmware { 1386 optee { 1387 compatible = "linaro,optee-tz"; 1388 method = "smc"; 1389 }; 1390 }; 1391}; 1392