1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree Include file for Layerscape-LX2160A family SoC. 4// 5// Copyright 2018-2020 NXP 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/memreserve/ 0x80000000 0x00010000; 11 12/ { 13 compatible = "fsl,lx2160a"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 rtc1 = &ftm_alarm0; 20 }; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 // 8 clusters having 2 Cortex-A72 cores each 27 cpu0: cpu@0 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a72"; 30 enable-method = "psci"; 31 reg = <0x0>; 32 clocks = <&clockgen 1 0>; 33 d-cache-size = <0x8000>; 34 d-cache-line-size = <64>; 35 d-cache-sets = <128>; 36 i-cache-size = <0xC000>; 37 i-cache-line-size = <64>; 38 i-cache-sets = <192>; 39 next-level-cache = <&cluster0_l2>; 40 cpu-idle-states = <&cpu_pw15>; 41 #cooling-cells = <2>; 42 }; 43 44 cpu1: cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a72"; 47 enable-method = "psci"; 48 reg = <0x1>; 49 clocks = <&clockgen 1 0>; 50 d-cache-size = <0x8000>; 51 d-cache-line-size = <64>; 52 d-cache-sets = <128>; 53 i-cache-size = <0xC000>; 54 i-cache-line-size = <64>; 55 i-cache-sets = <192>; 56 next-level-cache = <&cluster0_l2>; 57 cpu-idle-states = <&cpu_pw15>; 58 #cooling-cells = <2>; 59 }; 60 61 cpu100: cpu@100 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a72"; 64 enable-method = "psci"; 65 reg = <0x100>; 66 clocks = <&clockgen 1 1>; 67 d-cache-size = <0x8000>; 68 d-cache-line-size = <64>; 69 d-cache-sets = <128>; 70 i-cache-size = <0xC000>; 71 i-cache-line-size = <64>; 72 i-cache-sets = <192>; 73 next-level-cache = <&cluster1_l2>; 74 cpu-idle-states = <&cpu_pw15>; 75 #cooling-cells = <2>; 76 }; 77 78 cpu101: cpu@101 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a72"; 81 enable-method = "psci"; 82 reg = <0x101>; 83 clocks = <&clockgen 1 1>; 84 d-cache-size = <0x8000>; 85 d-cache-line-size = <64>; 86 d-cache-sets = <128>; 87 i-cache-size = <0xC000>; 88 i-cache-line-size = <64>; 89 i-cache-sets = <192>; 90 next-level-cache = <&cluster1_l2>; 91 cpu-idle-states = <&cpu_pw15>; 92 #cooling-cells = <2>; 93 }; 94 95 cpu200: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a72"; 98 enable-method = "psci"; 99 reg = <0x200>; 100 clocks = <&clockgen 1 2>; 101 d-cache-size = <0x8000>; 102 d-cache-line-size = <64>; 103 d-cache-sets = <128>; 104 i-cache-size = <0xC000>; 105 i-cache-line-size = <64>; 106 i-cache-sets = <192>; 107 next-level-cache = <&cluster2_l2>; 108 cpu-idle-states = <&cpu_pw15>; 109 #cooling-cells = <2>; 110 }; 111 112 cpu201: cpu@201 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a72"; 115 enable-method = "psci"; 116 reg = <0x201>; 117 clocks = <&clockgen 1 2>; 118 d-cache-size = <0x8000>; 119 d-cache-line-size = <64>; 120 d-cache-sets = <128>; 121 i-cache-size = <0xC000>; 122 i-cache-line-size = <64>; 123 i-cache-sets = <192>; 124 next-level-cache = <&cluster2_l2>; 125 cpu-idle-states = <&cpu_pw15>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu300: cpu@300 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a72"; 132 enable-method = "psci"; 133 reg = <0x300>; 134 clocks = <&clockgen 1 3>; 135 d-cache-size = <0x8000>; 136 d-cache-line-size = <64>; 137 d-cache-sets = <128>; 138 i-cache-size = <0xC000>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <192>; 141 next-level-cache = <&cluster3_l2>; 142 cpu-idle-states = <&cpu_pw15>; 143 #cooling-cells = <2>; 144 }; 145 146 cpu301: cpu@301 { 147 device_type = "cpu"; 148 compatible = "arm,cortex-a72"; 149 enable-method = "psci"; 150 reg = <0x301>; 151 clocks = <&clockgen 1 3>; 152 d-cache-size = <0x8000>; 153 d-cache-line-size = <64>; 154 d-cache-sets = <128>; 155 i-cache-size = <0xC000>; 156 i-cache-line-size = <64>; 157 i-cache-sets = <192>; 158 next-level-cache = <&cluster3_l2>; 159 cpu-idle-states = <&cpu_pw15>; 160 #cooling-cells = <2>; 161 }; 162 163 cpu400: cpu@400 { 164 device_type = "cpu"; 165 compatible = "arm,cortex-a72"; 166 enable-method = "psci"; 167 reg = <0x400>; 168 clocks = <&clockgen 1 4>; 169 d-cache-size = <0x8000>; 170 d-cache-line-size = <64>; 171 d-cache-sets = <128>; 172 i-cache-size = <0xC000>; 173 i-cache-line-size = <64>; 174 i-cache-sets = <192>; 175 next-level-cache = <&cluster4_l2>; 176 cpu-idle-states = <&cpu_pw15>; 177 #cooling-cells = <2>; 178 }; 179 180 cpu401: cpu@401 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a72"; 183 enable-method = "psci"; 184 reg = <0x401>; 185 clocks = <&clockgen 1 4>; 186 d-cache-size = <0x8000>; 187 d-cache-line-size = <64>; 188 d-cache-sets = <128>; 189 i-cache-size = <0xC000>; 190 i-cache-line-size = <64>; 191 i-cache-sets = <192>; 192 next-level-cache = <&cluster4_l2>; 193 cpu-idle-states = <&cpu_pw15>; 194 #cooling-cells = <2>; 195 }; 196 197 cpu500: cpu@500 { 198 device_type = "cpu"; 199 compatible = "arm,cortex-a72"; 200 enable-method = "psci"; 201 reg = <0x500>; 202 clocks = <&clockgen 1 5>; 203 d-cache-size = <0x8000>; 204 d-cache-line-size = <64>; 205 d-cache-sets = <128>; 206 i-cache-size = <0xC000>; 207 i-cache-line-size = <64>; 208 i-cache-sets = <192>; 209 next-level-cache = <&cluster5_l2>; 210 cpu-idle-states = <&cpu_pw15>; 211 #cooling-cells = <2>; 212 }; 213 214 cpu501: cpu@501 { 215 device_type = "cpu"; 216 compatible = "arm,cortex-a72"; 217 enable-method = "psci"; 218 reg = <0x501>; 219 clocks = <&clockgen 1 5>; 220 d-cache-size = <0x8000>; 221 d-cache-line-size = <64>; 222 d-cache-sets = <128>; 223 i-cache-size = <0xC000>; 224 i-cache-line-size = <64>; 225 i-cache-sets = <192>; 226 next-level-cache = <&cluster5_l2>; 227 cpu-idle-states = <&cpu_pw15>; 228 #cooling-cells = <2>; 229 }; 230 231 cpu600: cpu@600 { 232 device_type = "cpu"; 233 compatible = "arm,cortex-a72"; 234 enable-method = "psci"; 235 reg = <0x600>; 236 clocks = <&clockgen 1 6>; 237 d-cache-size = <0x8000>; 238 d-cache-line-size = <64>; 239 d-cache-sets = <128>; 240 i-cache-size = <0xC000>; 241 i-cache-line-size = <64>; 242 i-cache-sets = <192>; 243 next-level-cache = <&cluster6_l2>; 244 cpu-idle-states = <&cpu_pw15>; 245 #cooling-cells = <2>; 246 }; 247 248 cpu601: cpu@601 { 249 device_type = "cpu"; 250 compatible = "arm,cortex-a72"; 251 enable-method = "psci"; 252 reg = <0x601>; 253 clocks = <&clockgen 1 6>; 254 d-cache-size = <0x8000>; 255 d-cache-line-size = <64>; 256 d-cache-sets = <128>; 257 i-cache-size = <0xC000>; 258 i-cache-line-size = <64>; 259 i-cache-sets = <192>; 260 next-level-cache = <&cluster6_l2>; 261 cpu-idle-states = <&cpu_pw15>; 262 #cooling-cells = <2>; 263 }; 264 265 cpu700: cpu@700 { 266 device_type = "cpu"; 267 compatible = "arm,cortex-a72"; 268 enable-method = "psci"; 269 reg = <0x700>; 270 clocks = <&clockgen 1 7>; 271 d-cache-size = <0x8000>; 272 d-cache-line-size = <64>; 273 d-cache-sets = <128>; 274 i-cache-size = <0xC000>; 275 i-cache-line-size = <64>; 276 i-cache-sets = <192>; 277 next-level-cache = <&cluster7_l2>; 278 cpu-idle-states = <&cpu_pw15>; 279 #cooling-cells = <2>; 280 }; 281 282 cpu701: cpu@701 { 283 device_type = "cpu"; 284 compatible = "arm,cortex-a72"; 285 enable-method = "psci"; 286 reg = <0x701>; 287 clocks = <&clockgen 1 7>; 288 d-cache-size = <0x8000>; 289 d-cache-line-size = <64>; 290 d-cache-sets = <128>; 291 i-cache-size = <0xC000>; 292 i-cache-line-size = <64>; 293 i-cache-sets = <192>; 294 next-level-cache = <&cluster7_l2>; 295 cpu-idle-states = <&cpu_pw15>; 296 #cooling-cells = <2>; 297 }; 298 299 cluster0_l2: l2-cache0 { 300 compatible = "cache"; 301 cache-size = <0x100000>; 302 cache-line-size = <64>; 303 cache-sets = <1024>; 304 cache-level = <2>; 305 }; 306 307 cluster1_l2: l2-cache1 { 308 compatible = "cache"; 309 cache-size = <0x100000>; 310 cache-line-size = <64>; 311 cache-sets = <1024>; 312 cache-level = <2>; 313 }; 314 315 cluster2_l2: l2-cache2 { 316 compatible = "cache"; 317 cache-size = <0x100000>; 318 cache-line-size = <64>; 319 cache-sets = <1024>; 320 cache-level = <2>; 321 }; 322 323 cluster3_l2: l2-cache3 { 324 compatible = "cache"; 325 cache-size = <0x100000>; 326 cache-line-size = <64>; 327 cache-sets = <1024>; 328 cache-level = <2>; 329 }; 330 331 cluster4_l2: l2-cache4 { 332 compatible = "cache"; 333 cache-size = <0x100000>; 334 cache-line-size = <64>; 335 cache-sets = <1024>; 336 cache-level = <2>; 337 }; 338 339 cluster5_l2: l2-cache5 { 340 compatible = "cache"; 341 cache-size = <0x100000>; 342 cache-line-size = <64>; 343 cache-sets = <1024>; 344 cache-level = <2>; 345 }; 346 347 cluster6_l2: l2-cache6 { 348 compatible = "cache"; 349 cache-size = <0x100000>; 350 cache-line-size = <64>; 351 cache-sets = <1024>; 352 cache-level = <2>; 353 }; 354 355 cluster7_l2: l2-cache7 { 356 compatible = "cache"; 357 cache-size = <0x100000>; 358 cache-line-size = <64>; 359 cache-sets = <1024>; 360 cache-level = <2>; 361 }; 362 363 cpu_pw15: cpu-pw15 { 364 compatible = "arm,idle-state"; 365 idle-state-name = "PW15"; 366 arm,psci-suspend-param = <0x0>; 367 entry-latency-us = <2000>; 368 exit-latency-us = <2000>; 369 min-residency-us = <6000>; 370 }; 371 }; 372 373 gic: interrupt-controller@6000000 { 374 compatible = "arm,gic-v3"; 375 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 376 <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 377 // SGI_base) 378 <0x0 0x0c0c0000 0 0x2000>, // GICC 379 <0x0 0x0c0d0000 0 0x1000>, // GICH 380 <0x0 0x0c0e0000 0 0x20000>; // GICV 381 #interrupt-cells = <3>; 382 #address-cells = <2>; 383 #size-cells = <2>; 384 ranges; 385 interrupt-controller; 386 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 387 388 its: gic-its@6020000 { 389 compatible = "arm,gic-v3-its"; 390 msi-controller; 391 reg = <0x0 0x6020000 0 0x20000>; 392 }; 393 }; 394 395 timer { 396 compatible = "arm,armv8-timer"; 397 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 401 }; 402 403 pmu { 404 compatible = "arm,cortex-a72-pmu"; 405 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 406 }; 407 408 psci { 409 compatible = "arm,psci-0.2"; 410 method = "smc"; 411 }; 412 413 memory@80000000 { 414 // DRAM space - 1, size : 2 GB DRAM 415 device_type = "memory"; 416 reg = <0x00000000 0x80000000 0 0x80000000>; 417 }; 418 419 ddr1: memory-controller@1080000 { 420 compatible = "fsl,qoriq-memory-controller"; 421 reg = <0x0 0x1080000 0x0 0x1000>; 422 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 423 little-endian; 424 }; 425 426 ddr2: memory-controller@1090000 { 427 compatible = "fsl,qoriq-memory-controller"; 428 reg = <0x0 0x1090000 0x0 0x1000>; 429 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 430 little-endian; 431 }; 432 433 // One clock unit-sysclk node which bootloader require during DT fix-up 434 sysclk: sysclk { 435 compatible = "fixed-clock"; 436 #clock-cells = <0>; 437 clock-frequency = <100000000>; // fixed up by bootloader 438 clock-output-names = "sysclk"; 439 }; 440 441 thermal-zones { 442 core_thermal1: core-thermal1 { 443 polling-delay-passive = <1000>; 444 polling-delay = <5000>; 445 thermal-sensors = <&tmu 0>; 446 447 trips { 448 core_cluster_alert: core-cluster-alert { 449 temperature = <85000>; 450 hysteresis = <2000>; 451 type = "passive"; 452 }; 453 454 core_cluster_crit: core-cluster-crit { 455 temperature = <95000>; 456 hysteresis = <2000>; 457 type = "critical"; 458 }; 459 }; 460 461 }; 462 }; 463 464 soc { 465 compatible = "simple-bus"; 466 #address-cells = <2>; 467 #size-cells = <2>; 468 ranges; 469 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 470 471 crypto: crypto@8000000 { 472 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 473 fsl,sec-era = <10>; 474 #address-cells = <1>; 475 #size-cells = <1>; 476 ranges = <0x0 0x00 0x8000000 0x100000>; 477 reg = <0x00 0x8000000 0x0 0x100000>; 478 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 479 dma-coherent; 480 status = "disabled"; 481 482 sec_jr0: jr@10000 { 483 compatible = "fsl,sec-v5.0-job-ring", 484 "fsl,sec-v4.0-job-ring"; 485 reg = <0x10000 0x10000>; 486 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 487 status = "okay"; secure-status = "disabled"; /* NS-only */ 488 }; 489 490 sec_jr1: jr@20000 { 491 compatible = "fsl,sec-v5.0-job-ring", 492 "fsl,sec-v4.0-job-ring"; 493 reg = <0x20000 0x10000>; 494 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 495 status = "okay"; secure-status = "disabled"; /* NS-only */ 496 }; 497 498 sec_jr2: jr@30000 { 499 compatible = "fsl,sec-v5.0-job-ring", 500 "fsl,sec-v4.0-job-ring"; 501 reg = <0x30000 0x10000>; 502 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 503 status = "disabled"; secure-status = "okay"; /* S-only */ 504 }; 505 506 sec_jr3: jr@40000 { 507 compatible = "fsl,sec-v5.0-job-ring", 508 "fsl,sec-v4.0-job-ring"; 509 reg = <0x40000 0x10000>; 510 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 511 status = "okay"; secure-status = "disabled"; /* workaround for ATF */ 512 }; 513 }; 514 515 clockgen: clock-controller@1300000 { 516 compatible = "fsl,lx2160a-clockgen"; 517 reg = <0 0x1300000 0 0xa0000>; 518 #clock-cells = <2>; 519 clocks = <&sysclk>; 520 }; 521 522 dcfg: syscon@1e00000 { 523 compatible = "fsl,lx2160a-dcfg", "syscon"; 524 reg = <0x0 0x1e00000 0x0 0x10000>; 525 little-endian; 526 }; 527 528 sec_mon: sec-mon@1e90000 { 529 compatible = "fsl,lx2160a-sec-mon"; 530 reg = <0x0 0x1e90000 0x0 0x1000>; 531 status = "disabled"; 532 secure-status = "okay"; 533 }; 534 535 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 536 emdio1: mdio@8b96000 { 537 compatible = "fsl,fman-memac-mdio"; 538 reg = <0x0 0x8b96000 0x0 0x1000>; 539 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 little-endian; /* force the driver in LE mode */ 543 status = "disabled"; 544 }; 545 546 /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */ 547 emdio2: mdio@8b97000 { 548 compatible = "fsl,fman-memac-mdio"; 549 reg = <0x0 0x8b97000 0x0 0x1000>; 550 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 little-endian; /* force the driver in LE mode */ 554 status = "disabled"; 555 }; 556 557 i2c0: i2c@2000000 { 558 compatible = "fsl,vf610-i2c"; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 reg = <0x0 0x2000000 0x0 0x10000>; 562 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 563 clock-names = "i2c"; 564 clocks = <&clockgen 4 15>; 565 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 566 status = "disabled"; 567 }; 568 569 i2c1: i2c@2010000 { 570 compatible = "fsl,vf610-i2c"; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 reg = <0x0 0x2010000 0x0 0x10000>; 574 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 575 clock-names = "i2c"; 576 clocks = <&clockgen 4 15>; 577 status = "disabled"; 578 }; 579 580 i2c2: i2c@2020000 { 581 compatible = "fsl,vf610-i2c"; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 reg = <0x0 0x2020000 0x0 0x10000>; 585 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 586 clock-names = "i2c"; 587 clocks = <&clockgen 4 15>; 588 status = "disabled"; 589 }; 590 591 i2c3: i2c@2030000 { 592 compatible = "fsl,vf610-i2c"; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 reg = <0x0 0x2030000 0x0 0x10000>; 596 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 597 clock-names = "i2c"; 598 clocks = <&clockgen 4 15>; 599 status = "disabled"; 600 }; 601 602 i2c4: i2c@2040000 { 603 compatible = "fsl,vf610-i2c"; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 reg = <0x0 0x2040000 0x0 0x10000>; 607 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 608 clock-names = "i2c"; 609 clocks = <&clockgen 4 15>; 610 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 611 status = "disabled"; 612 }; 613 614 i2c5: i2c@2050000 { 615 compatible = "fsl,vf610-i2c"; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 reg = <0x0 0x2050000 0x0 0x10000>; 619 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 620 clock-names = "i2c"; 621 clocks = <&clockgen 4 15>; 622 status = "disabled"; 623 }; 624 625 i2c6: i2c@2060000 { 626 compatible = "fsl,vf610-i2c"; 627 #address-cells = <1>; 628 #size-cells = <0>; 629 reg = <0x0 0x2060000 0x0 0x10000>; 630 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 631 clock-names = "i2c"; 632 clocks = <&clockgen 4 15>; 633 status = "disabled"; 634 }; 635 636 i2c7: i2c@2070000 { 637 compatible = "fsl,vf610-i2c"; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 reg = <0x0 0x2070000 0x0 0x10000>; 641 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 642 clock-names = "i2c"; 643 clocks = <&clockgen 4 15>; 644 status = "disabled"; 645 }; 646 647 fspi: spi@20c0000 { 648 compatible = "nxp,lx2160a-fspi"; 649 #address-cells = <1>; 650 #size-cells = <0>; 651 reg = <0x0 0x20c0000 0x0 0x10000>, 652 <0x0 0x20000000 0x0 0x10000000>; 653 reg-names = "fspi_base", "fspi_mmap"; 654 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 656 clock-names = "fspi_en", "fspi"; 657 status = "disabled"; 658 }; 659 660 dspi0: spi@2100000 { 661 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 reg = <0x0 0x2100000 0x0 0x10000>; 665 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&clockgen 4 7>; 667 clock-names = "dspi"; 668 spi-num-chipselects = <5>; 669 bus-num = <0>; 670 status = "disabled"; 671 }; 672 673 dspi1: spi@2110000 { 674 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 reg = <0x0 0x2110000 0x0 0x10000>; 678 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&clockgen 4 7>; 680 clock-names = "dspi"; 681 spi-num-chipselects = <5>; 682 bus-num = <1>; 683 status = "disabled"; 684 }; 685 686 dspi2: spi@2120000 { 687 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 reg = <0x0 0x2120000 0x0 0x10000>; 691 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&clockgen 4 7>; 693 clock-names = "dspi"; 694 spi-num-chipselects = <5>; 695 bus-num = <2>; 696 status = "disabled"; 697 }; 698 699 esdhc0: esdhc@2140000 { 700 compatible = "fsl,esdhc"; 701 reg = <0x0 0x2140000 0x0 0x10000>; 702 interrupts = <0 28 0x4>; /* Level high type */ 703 clocks = <&clockgen 4 1>; 704 voltage-ranges = <1800 1800 3300 3300>; 705 sdhci,auto-cmd12; 706 little-endian; 707 bus-width = <4>; 708 status = "disabled"; 709 }; 710 711 esdhc1: esdhc@2150000 { 712 compatible = "fsl,esdhc"; 713 reg = <0x0 0x2150000 0x0 0x10000>; 714 interrupts = <0 63 0x4>; /* Level high type */ 715 clocks = <&clockgen 4 1>; 716 voltage-ranges = <1800 1800 3300 3300>; 717 sdhci,auto-cmd12; 718 broken-cd; 719 little-endian; 720 bus-width = <4>; 721 status = "disabled"; 722 }; 723 724 can0: can@2180000 { 725 compatible = "fsl,lx2160ar1-flexcan"; 726 reg = <0x0 0x2180000 0x0 0x10000>; 727 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&sysclk>, <&clockgen 4 7>; 729 clock-names = "ipg", "per"; 730 status = "disabled"; 731 }; 732 733 can1: can@2190000 { 734 compatible = "fsl,lx2160ar1-flexcan"; 735 reg = <0x0 0x2190000 0x0 0x10000>; 736 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&sysclk>, <&clockgen 4 7>; 738 clock-names = "ipg", "per"; 739 status = "disabled"; 740 }; 741 742 tmu: tmu@1f80000 { 743 compatible = "fsl,qoriq-tmu"; 744 reg = <0x0 0x1f80000 0x0 0x10000>; 745 interrupts = <0 23 0x4>; 746 fsl,tmu-range = <0x800000E6 0x8001017D>; 747 fsl,tmu-calibration = 748 /* Calibration data group 1 */ 749 <0x00000000 0x00000035 750 /* Calibration data group 2 */ 751 0x00010001 0x00000154>; 752 little-endian; 753 #thermal-sensor-cells = <1>; 754 }; 755 756 uart0: serial@21c0000 { 757 compatible = "arm,sbsa-uart","arm,pl011"; 758 reg = <0x0 0x21c0000 0x0 0x1000>; 759 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 760 current-speed = <115200>; 761 status = "disabled"; 762 }; 763 764 uart1: serial@21d0000 { 765 compatible = "arm,sbsa-uart","arm,pl011"; 766 reg = <0x0 0x21d0000 0x0 0x1000>; 767 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 768 current-speed = <115200>; 769 status = "disabled"; 770 }; 771 772 uart2: serial@21e0000 { 773 compatible = "arm,sbsa-uart","arm,pl011"; 774 reg = <0x0 0x21e0000 0x0 0x1000>; 775 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 776 current-speed = <115200>; 777 status = "disabled"; 778 }; 779 780 uart3: serial@21f0000 { 781 compatible = "arm,sbsa-uart","arm,pl011"; 782 reg = <0x0 0x21f0000 0x0 0x1000>; 783 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 784 current-speed = <115200>; 785 status = "disabled"; 786 }; 787 788 gpio0: gpio@2300000 { 789 compatible = "fsl,qoriq-gpio"; 790 reg = <0x0 0x2300000 0x0 0x10000>; 791 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 792 gpio-controller; 793 little-endian; 794 #gpio-cells = <2>; 795 interrupt-controller; 796 #interrupt-cells = <2>; 797 }; 798 799 gpio1: gpio@2310000 { 800 compatible = "fsl,qoriq-gpio"; 801 reg = <0x0 0x2310000 0x0 0x10000>; 802 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 803 gpio-controller; 804 little-endian; 805 #gpio-cells = <2>; 806 interrupt-controller; 807 #interrupt-cells = <2>; 808 }; 809 810 gpio2: gpio@2320000 { 811 compatible = "fsl,qoriq-gpio"; 812 reg = <0x0 0x2320000 0x0 0x10000>; 813 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 814 gpio-controller; 815 little-endian; 816 #gpio-cells = <2>; 817 interrupt-controller; 818 #interrupt-cells = <2>; 819 }; 820 821 gpio3: gpio@2330000 { 822 compatible = "fsl,qoriq-gpio"; 823 reg = <0x0 0x2330000 0x0 0x10000>; 824 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 825 gpio-controller; 826 little-endian; 827 #gpio-cells = <2>; 828 interrupt-controller; 829 #interrupt-cells = <2>; 830 }; 831 832 watchdog@23a0000 { 833 compatible = "arm,sbsa-gwdt"; 834 reg = <0x0 0x23a0000 0 0x1000>, 835 <0x0 0x2390000 0 0x1000>; 836 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 837 timeout-sec = <30>; 838 }; 839 840 rcpm: rcpm@1e34040 { 841 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; 842 reg = <0x0 0x1e34040 0x0 0x1c>; 843 #fsl,rcpm-wakeup-cells = <7>; 844 little-endian; 845 }; 846 847 ftm_alarm0: timer@2800000 { 848 compatible = "fsl,lx2160a-ftm-alarm"; 849 reg = <0x0 0x2800000 0x0 0x10000>; 850 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 851 interrupts = <0 44 4>; 852 }; 853 854 usb0: usb@3100000 { 855 compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; 856 reg = <0x0 0x3100000 0x0 0x10000>; 857 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 858 dr_mode = "host"; 859 snps,quirk-frame-length-adjustment = <0x20>; 860 usb3-lpm-capable; 861 snps,dis-u1u2-when-u3-quirk; 862 snps,dis_rxdet_inp3_quirk; 863 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 864 snps,host-vbus-glitches; 865 dma-coherent; 866 status = "disabled"; 867 }; 868 869 usb1: usb@3110000 { 870 compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; 871 reg = <0x0 0x3110000 0x0 0x10000>; 872 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 873 dr_mode = "host"; 874 snps,quirk-frame-length-adjustment = <0x20>; 875 usb3-lpm-capable; 876 snps,dis-u1u2-when-u3-quirk; 877 snps,dis_rxdet_inp3_quirk; 878 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 879 snps,host-vbus-glitches; 880 status = "disabled"; 881 }; 882 883 sata0: sata@3200000 { 884 compatible = "fsl,lx2160a-ahci"; 885 reg = <0x0 0x3200000 0x0 0x10000>, 886 <0x7 0x100520 0x0 0x4>; 887 reg-names = "ahci", "sata-ecc"; 888 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&clockgen 4 3>; 890 dma-coherent; 891 status = "disabled"; 892 }; 893 894 sata1: sata@3210000 { 895 compatible = "fsl,lx2160a-ahci"; 896 reg = <0x0 0x3210000 0x0 0x10000>, 897 <0x7 0x100520 0x0 0x4>; 898 reg-names = "ahci", "sata-ecc"; 899 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&clockgen 4 3>; 901 dma-coherent; 902 status = "disabled"; 903 }; 904 905 sata2: sata@3220000 { 906 compatible = "fsl,lx2160a-ahci"; 907 reg = <0x0 0x3220000 0x0 0x10000>, 908 <0x7 0x100520 0x0 0x4>; 909 reg-names = "ahci", "sata-ecc"; 910 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&clockgen 4 3>; 912 dma-coherent; 913 status = "disabled"; 914 }; 915 916 sata3: sata@3230000 { 917 compatible = "fsl,lx2160a-ahci"; 918 reg = <0x0 0x3230000 0x0 0x10000>, 919 <0x7 0x100520 0x0 0x4>; 920 reg-names = "ahci", "sata-ecc"; 921 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&clockgen 4 3>; 923 dma-coherent; 924 status = "disabled"; 925 }; 926 927 pcie@3400000 { 928 compatible = "fsl,lx2160a-pcie"; 929 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 930 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ 931 reg-names = "csr_axi_slave", "config_axi_slave"; 932 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 933 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 934 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 935 interrupt-names = "aer", "pme", "intr"; 936 #address-cells = <3>; 937 #size-cells = <2>; 938 device_type = "pci"; 939 dma-coherent; 940 apio-wins = <8>; 941 ppio-wins = <8>; 942 bus-range = <0x0 0xff>; 943 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 944 msi-parent = <&its>; 945 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 946 #interrupt-cells = <1>; 947 interrupt-map-mask = <0 0 0 7>; 948 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 949 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 950 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 951 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 952 status = "disabled"; 953 }; 954 955 pcie_ep@3400000 { 956 compatible = "fsl,lx2160a-pcie-ep"; 957 reg = <0x00 0x03400000 0x0 0x00100000 958 0x80 0x00000000 0x8 0x00000000>; 959 reg-names = "regs", "addr_space"; 960 num-ob-windows = <256>; 961 status = "disabled"; 962 }; 963 964 pcie@3500000 { 965 compatible = "fsl,lx2160a-pcie"; 966 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 967 0x88 0x00000000 0x0 0x00001000>; /* configuration space */ 968 reg-names = "csr_axi_slave", "config_axi_slave"; 969 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 970 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 971 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 972 interrupt-names = "aer", "pme", "intr"; 973 #address-cells = <3>; 974 #size-cells = <2>; 975 device_type = "pci"; 976 dma-coherent; 977 apio-wins = <8>; 978 ppio-wins = <8>; 979 bus-range = <0x0 0xff>; 980 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 981 msi-parent = <&its>; 982 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 983 #interrupt-cells = <1>; 984 interrupt-map-mask = <0 0 0 7>; 985 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 986 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 987 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 988 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 989 status = "disabled"; 990 }; 991 992 pcie_ep@3500000 { 993 compatible = "fsl,lx2160a-pcie-ep"; 994 reg = <0x00 0x03500000 0x0 0x00100000 995 0x88 0x00000000 0x8 0x00000000>; 996 reg-names = "regs", "addr_space"; 997 num-ob-windows = <256>; 998 status = "disabled"; 999 }; 1000 1001 pcie@3600000 { 1002 compatible = "fsl,lx2160a-pcie"; 1003 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 1004 0x90 0x00000000 0x0 0x00001000>; /* configuration space */ 1005 reg-names = "csr_axi_slave", "config_axi_slave"; 1006 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1007 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1008 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1009 interrupt-names = "aer", "pme", "intr"; 1010 #address-cells = <3>; 1011 #size-cells = <2>; 1012 device_type = "pci"; 1013 dma-coherent; 1014 apio-wins = <8>; 1015 ppio-wins = <8>; 1016 bus-range = <0x0 0xff>; 1017 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1018 msi-parent = <&its>; 1019 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1020 #interrupt-cells = <1>; 1021 interrupt-map-mask = <0 0 0 7>; 1022 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1023 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1024 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1025 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1026 status = "disabled"; 1027 }; 1028 1029 pcie_ep@3600000 { 1030 compatible = "fsl,lx2160a-pcie-ep"; 1031 reg = <0x00 0x03600000 0x0 0x00100000 1032 0x90 0x00000000 0x8 0x00000000>; 1033 reg-names = "regs", "addr_space"; 1034 num-ob-windows = <256>; 1035 max-functions = <2>; 1036 status = "disabled"; 1037 }; 1038 1039 pcie@3700000 { 1040 compatible = "fsl,lx2160a-pcie"; 1041 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 1042 0x98 0x00000000 0x0 0x00001000>; /* configuration space */ 1043 reg-names = "csr_axi_slave", "config_axi_slave"; 1044 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1045 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1046 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1047 interrupt-names = "aer", "pme", "intr"; 1048 #address-cells = <3>; 1049 #size-cells = <2>; 1050 device_type = "pci"; 1051 dma-coherent; 1052 apio-wins = <8>; 1053 ppio-wins = <8>; 1054 bus-range = <0x0 0xff>; 1055 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1056 msi-parent = <&its>; 1057 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1058 #interrupt-cells = <1>; 1059 interrupt-map-mask = <0 0 0 7>; 1060 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1061 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1062 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1063 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1064 status = "disabled"; 1065 }; 1066 1067 pcie_ep@3700000 { 1068 compatible = "fsl,lx2160a-pcie-ep"; 1069 reg = <0x00 0x03700000 0x0 0x00100000 1070 0x98 0x00000000 0x8 0x00000000>; 1071 reg-names = "regs", "addr_space"; 1072 num-ob-windows = <256>; 1073 status = "disabled"; 1074 }; 1075 1076 pcie@3800000 { 1077 compatible = "fsl,lx2160a-pcie"; 1078 reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ 1079 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */ 1080 reg-names = "csr_axi_slave", "config_axi_slave"; 1081 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1082 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1083 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1084 interrupt-names = "aer", "pme", "intr"; 1085 #address-cells = <3>; 1086 #size-cells = <2>; 1087 device_type = "pci"; 1088 dma-coherent; 1089 apio-wins = <8>; 1090 ppio-wins = <8>; 1091 bus-range = <0x0 0xff>; 1092 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1093 msi-parent = <&its>; 1094 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1095 #interrupt-cells = <1>; 1096 interrupt-map-mask = <0 0 0 7>; 1097 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1098 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1099 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1100 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1101 status = "disabled"; 1102 }; 1103 1104 pcie_ep@3800000 { 1105 compatible = "fsl,lx2160a-pcie-ep"; 1106 reg = <0x00 0x03800000 0x0 0x00100000 1107 0xa0 0x00000000 0x8 0x00000000>; 1108 reg-names = "regs", "addr_space"; 1109 num-ob-windows = <256>; 1110 max-functions = <2>; 1111 status = "disabled"; 1112 }; 1113 1114 pcie@3900000 { 1115 compatible = "fsl,lx2160a-pcie"; 1116 reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ 1117 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */ 1118 reg-names = "csr_axi_slave", "config_axi_slave"; 1119 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1120 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1121 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1122 interrupt-names = "aer", "pme", "intr"; 1123 #address-cells = <3>; 1124 #size-cells = <2>; 1125 device_type = "pci"; 1126 dma-coherent; 1127 apio-wins = <8>; 1128 ppio-wins = <8>; 1129 bus-range = <0x0 0xff>; 1130 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1131 msi-parent = <&its>; 1132 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1133 #interrupt-cells = <1>; 1134 interrupt-map-mask = <0 0 0 7>; 1135 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1136 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1137 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1138 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1139 status = "disabled"; 1140 }; 1141 1142 pcie_ep@3900000 { 1143 compatible = "fsl,lx2160a-pcie-ep"; 1144 reg = <0x00 0x03900000 0x0 0x00100000 1145 0xa8 0x00000000 0x8 0x00000000>; 1146 reg-names = "regs", "addr_space"; 1147 num-ob-windows = <256>; 1148 status = "disabled"; 1149 }; 1150 1151 smmu: iommu@5000000 { 1152 compatible = "arm,mmu-500"; 1153 reg = <0 0x5000000 0 0x800000>; 1154 #iommu-cells = <1>; 1155 #global-interrupts = <14>; 1156 // global secure fault 1157 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1158 // combined secure 1159 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1160 // global non-secure fault 1161 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1162 // combined non-secure 1163 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1164 // performance counter interrupts 0-9 1165 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1175 // per context interrupt, 64 interrupts 1176 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1240 dma-coherent; 1241 }; 1242 1243 console@8340020 { 1244 compatible = "fsl,dpaa2-console"; 1245 reg = <0x00000000 0x08340020 0 0x2>; 1246 }; 1247 1248 ptp-timer@8b95000 { 1249 compatible = "fsl,dpaa2-ptp"; 1250 reg = <0x0 0x8b95000 0x0 0x100>; 1251 clocks = <&clockgen 4 1>; 1252 little-endian; 1253 fsl,extts-fifo; 1254 }; 1255 1256 fsl_mc: fsl-mc@80c000000 { 1257 compatible = "fsl,qoriq-mc"; 1258 reg = <0x00000008 0x0c000000 0 0x40>, 1259 <0x00000000 0x08340000 0 0x40000>; 1260 msi-parent = <&its>; 1261 /* iommu-map property is fixed up by u-boot */ 1262 iommu-map = <0 &smmu 0 0>; 1263 dma-coherent; 1264 #address-cells = <3>; 1265 #size-cells = <1>; 1266 1267 /* 1268 * Region type 0x0 - MC portals 1269 * Region type 0x1 - QBMAN portals 1270 */ 1271 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 1272 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 1273 1274 /* 1275 * Define the maximum number of MACs present on the SoC. 1276 */ 1277 dpmacs { 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 1281 dpmac1: dpmac@1 { 1282 compatible = "fsl,qoriq-mc-dpmac"; 1283 reg = <0x1>; 1284 }; 1285 1286 dpmac2: dpmac@2 { 1287 compatible = "fsl,qoriq-mc-dpmac"; 1288 reg = <0x2>; 1289 }; 1290 1291 dpmac3: dpmac@3 { 1292 compatible = "fsl,qoriq-mc-dpmac"; 1293 reg = <0x3>; 1294 }; 1295 1296 dpmac4: dpmac@4 { 1297 compatible = "fsl,qoriq-mc-dpmac"; 1298 reg = <0x4>; 1299 }; 1300 1301 dpmac5: dpmac@5 { 1302 compatible = "fsl,qoriq-mc-dpmac"; 1303 reg = <0x5>; 1304 }; 1305 1306 dpmac6: dpmac@6 { 1307 compatible = "fsl,qoriq-mc-dpmac"; 1308 reg = <0x6>; 1309 }; 1310 1311 dpmac7: dpmac@7 { 1312 compatible = "fsl,qoriq-mc-dpmac"; 1313 reg = <0x7>; 1314 }; 1315 1316 dpmac8: dpmac@8 { 1317 compatible = "fsl,qoriq-mc-dpmac"; 1318 reg = <0x8>; 1319 }; 1320 1321 dpmac9: dpmac@9 { 1322 compatible = "fsl,qoriq-mc-dpmac"; 1323 reg = <0x9>; 1324 }; 1325 1326 dpmac10: dpmac@a { 1327 compatible = "fsl,qoriq-mc-dpmac"; 1328 reg = <0xa>; 1329 }; 1330 1331 dpmac11: dpmac@b { 1332 compatible = "fsl,qoriq-mc-dpmac"; 1333 reg = <0xb>; 1334 }; 1335 1336 dpmac12: dpmac@c { 1337 compatible = "fsl,qoriq-mc-dpmac"; 1338 reg = <0xc>; 1339 }; 1340 1341 dpmac13: dpmac@d { 1342 compatible = "fsl,qoriq-mc-dpmac"; 1343 reg = <0xd>; 1344 }; 1345 1346 dpmac14: dpmac@e { 1347 compatible = "fsl,qoriq-mc-dpmac"; 1348 reg = <0xe>; 1349 }; 1350 1351 dpmac15: dpmac@f { 1352 compatible = "fsl,qoriq-mc-dpmac"; 1353 reg = <0xf>; 1354 }; 1355 1356 dpmac16: dpmac@10 { 1357 compatible = "fsl,qoriq-mc-dpmac"; 1358 reg = <0x10>; 1359 }; 1360 1361 dpmac17: dpmac@11 { 1362 compatible = "fsl,qoriq-mc-dpmac"; 1363 reg = <0x11>; 1364 }; 1365 1366 dpmac18: dpmac@12 { 1367 compatible = "fsl,qoriq-mc-dpmac"; 1368 reg = <0x12>; 1369 }; 1370 }; 1371 }; 1372 }; 1373 1374 firmware { 1375 optee { 1376 compatible = "linaro,optee-tz"; 1377 method = "smc"; 1378 }; 1379 }; 1380}; 1381