1# Setup compiler for the core module 2ifeq ($(CFG_ARM64_core),y) 3arch-bits-core := 64 4else 5arch-bits-core := 32 6endif 7CROSS_COMPILE_core := $(CROSS_COMPILE$(arch-bits-core)) 8COMPILER_core := $(COMPILER) 9include mk/$(COMPILER_core).mk 10 11# Defines the cc-option macro using the compiler set for the core module 12include mk/cc-option.mk 13 14# Size of emulated TrustZone protected SRAM, 448 kB. 15# Only applicable when paging is enabled. 16CFG_CORE_TZSRAM_EMUL_SIZE ?= 458752 17 18ifneq ($(CFG_LPAE_ADDR_SPACE_SIZE),) 19$(warning Error: CFG_LPAE_ADDR_SPACE_SIZE is not supported any longer) 20$(error Error: Please use CFG_LPAE_ADDR_SPACE_BITS instead) 21endif 22 23CFG_LPAE_ADDR_SPACE_BITS ?= 32 24 25CFG_MMAP_REGIONS ?= 13 26CFG_RESERVED_VASPACE_SIZE ?= (1024 * 1024 * 10) 27 28ifeq ($(CFG_ARM64_core),y) 29ifeq ($(CFG_ARM32_core),y) 30$(error CFG_ARM64_core and CFG_ARM32_core cannot be both 'y') 31endif 32CFG_KERN_LINKER_FORMAT ?= elf64-littleaarch64 33CFG_KERN_LINKER_ARCH ?= aarch64 34# TCR_EL1.IPS needs to be initialized according to the largest physical 35# address that we need to map. 36# Physical address size 37# 32 bits, 4GB. 38# 36 bits, 64GB. 39# (etc.) 40CFG_CORE_ARM64_PA_BITS ?= 32 41$(call force,CFG_WITH_LPAE,y) 42else 43$(call force,CFG_ARM32_core,y) 44CFG_KERN_LINKER_FORMAT ?= elf32-littlearm 45CFG_KERN_LINKER_ARCH ?= arm 46endif 47 48ifeq ($(CFG_TA_FLOAT_SUPPORT),y) 49# Use hard-float for floating point support in user TAs instead of 50# soft-float 51CFG_WITH_VFP ?= y 52ifeq ($(CFG_ARM64_core),y) 53# AArch64 has no fallback to soft-float 54$(call force,CFG_WITH_VFP,y) 55endif 56ifeq ($(CFG_WITH_VFP),y) 57arm64-platform-hard-float-enabled := y 58ifneq ($(CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT),y) 59arm32-platform-hard-float-enabled := y 60endif 61endif 62endif 63 64# Adds protection against CVE-2017-5715 also know as Spectre 65# (https://spectreattack.com) 66# See also https://developer.arm.com/-/media/Files/pdf/Cache_Speculation_Side-channels.pdf 67# Variant 2 68CFG_CORE_WORKAROUND_SPECTRE_BP ?= y 69# Same as CFG_CORE_WORKAROUND_SPECTRE_BP but targeting exceptions from 70# secure EL0 instead of non-secure world, including mitigation for 71# CVE-2022-23960. 72CFG_CORE_WORKAROUND_SPECTRE_BP_SEC ?= $(CFG_CORE_WORKAROUND_SPECTRE_BP) 73 74# Adds protection against a tool like Cachegrab 75# (https://github.com/nccgroup/cachegrab), which uses non-secure interrupts 76# to prime and later analyze the L1D, L1I and BTB caches to gain 77# information from secure world execution. 78CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME ?= y 79ifeq ($(CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME),y) 80$(call force,CFG_CORE_WORKAROUND_SPECTRE_BP,y,Required by CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME) 81endif 82 83CFG_CORE_RWDATA_NOEXEC ?= y 84CFG_CORE_RODATA_NOEXEC ?= n 85ifeq ($(CFG_CORE_RODATA_NOEXEC),y) 86$(call force,CFG_CORE_RWDATA_NOEXEC,y) 87endif 88# 'y' to set the Alignment Check Enable bit in SCTLR/SCTLR_EL1, 'n' to clear it 89CFG_SCTLR_ALIGNMENT_CHECK ?= n 90 91ifeq ($(CFG_CORE_LARGE_PHYS_ADDR),y) 92$(call force,CFG_WITH_LPAE,y) 93endif 94 95# SPMC configuration "S-EL1 SPMC" where SPM Core is implemented at S-EL1, 96# that is, OP-TEE. 97ifeq ($(CFG_CORE_SEL1_SPMC),y) 98$(call force,CFG_CORE_FFA,y) 99$(call force,CFG_CORE_SEL2_SPMC,n) 100$(call force,CFG_CORE_EL3_SPMC,n) 101endif 102# SPMC configuration "S-EL2 SPMC" where SPM Core is implemented at S-EL2, 103# that is, the hypervisor sandboxing OP-TEE 104ifeq ($(CFG_CORE_SEL2_SPMC),y) 105$(call force,CFG_CORE_FFA,y) 106$(call force,CFG_CORE_SEL1_SPMC,n) 107$(call force,CFG_CORE_EL3_SPMC,n) 108endif 109# SPMC configuration "EL3 SPMC" where SPM Core is implemented at EL3, that 110# is, in TF-A 111ifeq ($(CFG_CORE_EL3_SPMC),y) 112$(call force,CFG_CORE_FFA,y) 113$(call force,CFG_CORE_SEL2_SPMC,n) 114$(call force,CFG_CORE_SEL1_SPMC,n) 115endif 116 117# Unmaps all kernel mode code except the code needed to take exceptions 118# from user space and restore kernel mode mapping again. This gives more 119# strict control over what is accessible while in user mode. 120# Addresses CVE-2017-5715 (aka Meltdown) known to affect Arm Cortex-A75 121CFG_CORE_UNMAP_CORE_AT_EL0 ?= y 122 123# Initialize PMCR.DP to 1 to prohibit cycle counting in secure state, and 124# save/restore PMCR during world switch. 125CFG_SM_NO_CYCLE_COUNTING ?= y 126 127 128# CFG_CORE_ASYNC_NOTIF_GIC_INTID is defined by the platform to some free 129# interrupt. Setting it to a non-zero number enables support for using an 130# Arm-GIC to notify normal world. This config variable should use a value 131# larger the 32 to make it of the type SPI. 132# Note that asynchronous notifactions must be enabled with 133# CFG_CORE_ASYNC_NOTIF=y for this variable to be used. 134CFG_CORE_ASYNC_NOTIF_GIC_INTID ?= 0 135 136ifeq ($(CFG_ARM32_core),y) 137# Configration directive related to ARMv7 optee boot arguments. 138# CFG_PAGEABLE_ADDR: if defined, forces pageable data physical address. 139# CFG_NS_ENTRY_ADDR: if defined, forces NS World physical entry address. 140# CFG_DT_ADDR: if defined, forces Device Tree data physical address. 141endif 142 143# CFG_MAX_CACHE_LINE_SHIFT is used to define platform specific maximum cache 144# line size in address lines. This must cover all inner and outer cache levels. 145# When data is aligned with this and cache operations are performed then those 146# only affect correct data. 147# 148# Default value (6 lines or 64 bytes) should cover most architectures, override 149# this in platform config if different. 150CFG_MAX_CACHE_LINE_SHIFT ?= 6 151 152core-platform-cppflags += -I$(arch-dir)/include 153core-platform-subdirs += \ 154 $(addprefix $(arch-dir)/, kernel crypto mm tee) $(platform-dir) 155 156ifneq ($(CFG_WITH_ARM_TRUSTED_FW),y) 157core-platform-subdirs += $(arch-dir)/sm 158endif 159 160arm64-platform-cppflags += -DARM64=1 -D__LP64__=1 161arm32-platform-cppflags += -DARM32=1 -D__ILP32__=1 162 163platform-cflags-generic ?= -ffunction-sections -fdata-sections -pipe 164platform-aflags-generic ?= -pipe 165 166arm32-platform-aflags += -marm 167 168arm32-platform-cflags-no-hard-float ?= -mfloat-abi=soft 169arm32-platform-cflags-hard-float ?= -mfloat-abi=hard -funsafe-math-optimizations 170arm32-platform-cflags-generic-thumb ?= -mthumb \ 171 -fno-short-enums -fno-common -mno-unaligned-access 172arm32-platform-cflags-generic-arm ?= -marm -fno-omit-frame-pointer -mapcs \ 173 -fno-short-enums -fno-common -mno-unaligned-access 174arm32-platform-aflags-no-hard-float ?= 175 176arm64-platform-cflags-no-hard-float ?= -mgeneral-regs-only 177arm64-platform-cflags-hard-float ?= 178arm64-platform-cflags-generic := -mstrict-align $(call cc-option,-mno-outline-atomics,) 179 180ifeq ($(CFG_MEMTAG),y) 181arm64-platform-cflags += -march=armv8.5-a+memtag 182arm64-platform-aflags += -march=armv8.5-a+memtag 183endif 184 185platform-cflags-optimization ?= -O$(CFG_CC_OPT_LEVEL) 186 187ifeq ($(CFG_DEBUG_INFO),y) 188platform-cflags-debug-info ?= -g3 189platform-aflags-debug-info ?= -g 190endif 191 192core-platform-cflags += $(platform-cflags-optimization) 193core-platform-cflags += $(platform-cflags-generic) 194core-platform-cflags += $(platform-cflags-debug-info) 195 196core-platform-aflags += $(platform-aflags-generic) 197core-platform-aflags += $(platform-aflags-debug-info) 198 199ifeq ($(CFG_CORE_ASLR),y) 200core-platform-cflags += -fpie 201endif 202 203ifeq ($(CFG_CORE_PAUTH),y) 204bp-core-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf) 205endif 206 207ifeq ($(CFG_CORE_BTI),y) 208bp-core-opt := $(call cc-option,-mbranch-protection=bti) 209endif 210 211ifeq (y-y,$(CFG_CORE_PAUTH)-$(CFG_CORE_BTI)) 212bp-core-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf+bti) 213endif 214 215ifeq (y,$(filter $(CFG_CORE_BTI) $(CFG_CORE_PAUTH),y)) 216ifeq (,$(bp-core-opt)) 217$(error -mbranch-protection not supported) 218endif 219core-platform-cflags += $(bp-core-opt) 220endif 221 222ifeq ($(CFG_ARM64_core),y) 223core-platform-cppflags += $(arm64-platform-cppflags) 224core-platform-cflags += $(arm64-platform-cflags) 225core-platform-cflags += $(arm64-platform-cflags-generic) 226core-platform-cflags += $(arm64-platform-cflags-no-hard-float) 227core-platform-aflags += $(arm64-platform-aflags) 228else 229core-platform-cppflags += $(arm32-platform-cppflags) 230core-platform-cflags += $(arm32-platform-cflags) 231core-platform-cflags += $(arm32-platform-cflags-no-hard-float) 232ifeq ($(CFG_UNWIND),y) 233core-platform-cflags += -funwind-tables 234endif 235ifeq ($(CFG_SYSCALL_FTRACE),y) 236core-platform-cflags += $(arm32-platform-cflags-generic-arm) 237else 238core-platform-cflags += $(arm32-platform-cflags-generic-thumb) 239endif 240core-platform-aflags += $(core_arm32-platform-aflags) 241core-platform-aflags += $(arm32-platform-aflags) 242endif 243 244# Provide default supported-ta-targets if not set by the platform config 245ifeq (,$(supported-ta-targets)) 246supported-ta-targets = ta_arm32 247ifeq ($(CFG_ARM64_core),y) 248supported-ta-targets += ta_arm64 249endif 250endif 251 252ta-targets := $(if $(CFG_USER_TA_TARGETS),$(filter $(supported-ta-targets),$(CFG_USER_TA_TARGETS)),$(supported-ta-targets)) 253unsup-targets := $(filter-out $(ta-targets),$(CFG_USER_TA_TARGETS)) 254ifneq (,$(unsup-targets)) 255$(error CFG_USER_TA_TARGETS contains unsupported value(s): $(unsup-targets). Valid values: $(supported-ta-targets)) 256endif 257 258ifneq ($(filter ta_arm32,$(ta-targets)),) 259# Variables for ta-target/sm "ta_arm32" 260CFG_ARM32_ta_arm32 := y 261arch-bits-ta_arm32 := 32 262ta_arm32-platform-cppflags += $(arm32-platform-cppflags) 263ta_arm32-platform-cflags += $(arm32-platform-cflags) 264ta_arm32-platform-cflags += $(platform-cflags-optimization) 265ta_arm32-platform-cflags += $(platform-cflags-debug-info) 266ta_arm32-platform-cflags += -fpic 267 268# Thumb mode doesn't support function graph tracing due to missing 269# frame pointer support required to trace function call chain. So 270# rather compile in ARM mode if function tracing is enabled. 271ifeq ($(CFG_FTRACE_SUPPORT),y) 272ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-arm) 273else 274ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-thumb) 275endif 276 277ifeq ($(arm32-platform-hard-float-enabled),y) 278ta_arm32-platform-cflags += $(arm32-platform-cflags-hard-float) 279else 280ta_arm32-platform-cflags += $(arm32-platform-cflags-no-hard-float) 281endif 282ifeq ($(CFG_UNWIND),y) 283ta_arm32-platform-cflags += -funwind-tables 284endif 285ta_arm32-platform-aflags += $(platform-aflags-generic) 286ta_arm32-platform-aflags += $(platform-aflags-debug-info) 287ta_arm32-platform-aflags += $(arm32-platform-aflags) 288 289ta_arm32-platform-cxxflags += -fpic 290ta_arm32-platform-cxxflags += $(arm32-platform-cxxflags) 291ta_arm32-platform-cxxflags += $(platform-cflags-optimization) 292ta_arm32-platform-cxxflags += $(platform-cflags-debug-info) 293 294ifeq ($(arm32-platform-hard-float-enabled),y) 295ta_arm32-platform-cxxflags += $(arm32-platform-cflags-hard-float) 296else 297ta_arm32-platform-cxxflags += $(arm32-platform-cflags-no-hard-float) 298endif 299 300ta-mk-file-export-vars-ta_arm32 += CFG_ARM32_ta_arm32 301ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cppflags 302ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cflags 303ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-aflags 304ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cxxflags 305 306ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE ?= arm-linux-gnueabihf-_nl_ 307ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE32 ?= $$(CROSS_COMPILE)_nl_ 308ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE_ta_arm32 ?= $$(CROSS_COMPILE32)_nl_ 309ta-mk-file-export-add-ta_arm32 += COMPILER ?= gcc_nl_ 310ta-mk-file-export-add-ta_arm32 += COMPILER_ta_arm32 ?= $$(COMPILER)_nl_ 311ta-mk-file-export-add-ta_arm32 += PYTHON3 ?= python3_nl_ 312endif 313 314ifneq ($(filter ta_arm64,$(ta-targets)),) 315# Variables for ta-target/sm "ta_arm64" 316CFG_ARM64_ta_arm64 := y 317arch-bits-ta_arm64 := 64 318ta_arm64-platform-cppflags += $(arm64-platform-cppflags) 319ta_arm64-platform-cflags += $(arm64-platform-cflags) 320ta_arm64-platform-cflags += $(platform-cflags-optimization) 321ta_arm64-platform-cflags += $(platform-cflags-debug-info) 322ta_arm64-platform-cflags += -fpic 323ta_arm64-platform-cflags += $(arm64-platform-cflags-generic) 324ifeq ($(arm64-platform-hard-float-enabled),y) 325ta_arm64-platform-cflags += $(arm64-platform-cflags-hard-float) 326else 327ta_arm64-platform-cflags += $(arm64-platform-cflags-no-hard-float) 328endif 329ta_arm64-platform-aflags += $(platform-aflags-generic) 330ta_arm64-platform-aflags += $(platform-aflags-debug-info) 331ta_arm64-platform-aflags += $(arm64-platform-aflags) 332 333ta_arm64-platform-cxxflags += -fpic 334ta_arm64-platform-cxxflags += $(platform-cflags-optimization) 335ta_arm64-platform-cxxflags += $(platform-cflags-debug-info) 336 337ifeq ($(CFG_TA_PAUTH),y) 338bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf) 339endif 340 341ifeq ($(CFG_TA_BTI),y) 342bp-ta-opt := $(call cc-option,-mbranch-protection=bti) 343endif 344 345ifeq (y-y,$(CFG_TA_PAUTH)-$(CFG_TA_BTI)) 346bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf+bti) 347endif 348 349ifeq (y,$(filter $(CFG_TA_BTI) $(CFG_TA_PAUTH),y)) 350ifeq (,$(bp-ta-opt)) 351$(error -mbranch-protection not supported) 352endif 353ta_arm64-platform-cflags += $(bp-ta-opt) 354endif 355 356ta-mk-file-export-vars-ta_arm64 += CFG_ARM64_ta_arm64 357ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cppflags 358ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cflags 359ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-aflags 360ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cxxflags 361 362ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE64 ?= $$(CROSS_COMPILE)_nl_ 363ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE_ta_arm64 ?= $$(CROSS_COMPILE64)_nl_ 364ta-mk-file-export-add-ta_arm64 += COMPILER ?= gcc_nl_ 365ta-mk-file-export-add-ta_arm64 += COMPILER_ta_arm64 ?= $$(COMPILER)_nl_ 366ta-mk-file-export-add-ta_arm64 += PYTHON3 ?= python3_nl_ 367endif 368 369# Set cross compiler prefix for each TA target 370$(foreach sm, $(ta-targets), $(eval CROSS_COMPILE_$(sm) ?= $(CROSS_COMPILE$(arch-bits-$(sm))))) 371 372arm32-sysreg-txt = core/arch/arm/kernel/arm32_sysreg.txt 373arm32-sysregs-$(arm32-sysreg-txt)-h := arm32_sysreg.h 374arm32-sysregs-$(arm32-sysreg-txt)-s := arm32_sysreg.S 375arm32-sysregs += $(arm32-sysreg-txt) 376 377ifeq ($(CFG_ARM_GICV3),y) 378arm32-gicv3-sysreg-txt = core/arch/arm/kernel/arm32_gicv3_sysreg.txt 379arm32-sysregs-$(arm32-gicv3-sysreg-txt)-h := arm32_gicv3_sysreg.h 380arm32-sysregs-$(arm32-gicv3-sysreg-txt)-s := arm32_gicv3_sysreg.S 381arm32-sysregs += $(arm32-gicv3-sysreg-txt) 382endif 383 384arm32-sysregs-out := $(out-dir)/$(sm)/include/generated 385 386define process-arm32-sysreg 387FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 388cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 389 390$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h): $(1) scripts/arm32_sysreg.py 391 @$(cmd-echo-silent) ' GEN $$@' 392 $(q)mkdir -p $$(dir $$@) 393 $(q)scripts/arm32_sysreg.py --guard __$$(arm32-sysregs-$(1)-h) \ 394 < $$< > $$@ 395 396FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 397cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 398 399$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s): $(1) scripts/arm32_sysreg.py 400 @$(cmd-echo-silent) ' GEN $$@' 401 $(q)mkdir -p $$(dir $$@) 402 $(q)scripts/arm32_sysreg.py --s_file < $$< > $$@ 403endef #process-arm32-sysreg 404 405$(foreach sr, $(arm32-sysregs), $(eval $(call process-arm32-sysreg,$(sr)))) 406