1# Setup compiler for the core module 2ifeq ($(CFG_ARM64_core),y) 3arch-bits-core := 64 4else 5arch-bits-core := 32 6endif 7CROSS_COMPILE_core := $(CROSS_COMPILE$(arch-bits-core)) 8COMPILER_core := $(COMPILER) 9include mk/$(COMPILER_core).mk 10 11# Defines the cc-option macro using the compiler set for the core module 12include mk/cc-option.mk 13 14# Size of emulated TrustZone protected SRAM, 448 kB. 15# Only applicable when paging is enabled. 16CFG_CORE_TZSRAM_EMUL_SIZE ?= 458752 17 18ifneq ($(CFG_LPAE_ADDR_SPACE_SIZE),) 19$(warning Error: CFG_LPAE_ADDR_SPACE_SIZE is not supported any longer) 20$(error Error: Please use CFG_LPAE_ADDR_SPACE_BITS instead) 21endif 22 23CFG_LPAE_ADDR_SPACE_BITS ?= 32 24 25CFG_MMAP_REGIONS ?= 13 26CFG_RESERVED_VASPACE_SIZE ?= (1024 * 1024 * 10) 27 28ifeq ($(CFG_ARM64_core),y) 29CFG_KERN_LINKER_FORMAT ?= elf64-littleaarch64 30CFG_KERN_LINKER_ARCH ?= aarch64 31# TCR_EL1.IPS needs to be initialized according to the largest physical 32# address that we need to map. 33# Physical address size 34# 32 bits, 4GB. 35# 36 bits, 64GB. 36# (etc.) 37CFG_CORE_ARM64_PA_BITS ?= 32 38else 39ifeq ($(CFG_ARM32_core),y) 40CFG_KERN_LINKER_FORMAT ?= elf32-littlearm 41CFG_KERN_LINKER_ARCH ?= arm 42else 43$(error Error: CFG_ARM64_core or CFG_ARM32_core should be defined) 44endif 45endif 46 47ifeq ($(CFG_TA_FLOAT_SUPPORT),y) 48# Use hard-float for floating point support in user TAs instead of 49# soft-float 50CFG_WITH_VFP ?= y 51ifeq ($(CFG_ARM64_core),y) 52# AArch64 has no fallback to soft-float 53$(call force,CFG_WITH_VFP,y) 54endif 55ifeq ($(CFG_WITH_VFP),y) 56arm64-platform-hard-float-enabled := y 57ifneq ($(CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT),y) 58arm32-platform-hard-float-enabled := y 59endif 60endif 61endif 62 63# Adds protection against CVE-2017-5715 also know as Spectre 64# (https://spectreattack.com) 65# See also https://developer.arm.com/-/media/Files/pdf/Cache_Speculation_Side-channels.pdf 66# Variant 2 67CFG_CORE_WORKAROUND_SPECTRE_BP ?= y 68# Same as CFG_CORE_WORKAROUND_SPECTRE_BP but targeting exceptions from 69# secure EL0 instead of non-secure world. 70CFG_CORE_WORKAROUND_SPECTRE_BP_SEC ?= $(CFG_CORE_WORKAROUND_SPECTRE_BP) 71 72# Adds protection against a tool like Cachegrab 73# (https://github.com/nccgroup/cachegrab), which uses non-secure interrupts 74# to prime and later analyze the L1D, L1I and BTB caches to gain 75# information from secure world execution. 76CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME ?= y 77ifeq ($(CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME),y) 78$(call force,CFG_CORE_WORKAROUND_SPECTRE_BP,y,Required by CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME) 79endif 80 81CFG_CORE_RWDATA_NOEXEC ?= y 82CFG_CORE_RODATA_NOEXEC ?= n 83ifeq ($(CFG_CORE_RODATA_NOEXEC),y) 84$(call force,CFG_CORE_RWDATA_NOEXEC,y) 85endif 86# 'y' to set the Alignment Check Enable bit in SCTLR/SCTLR_EL1, 'n' to clear it 87CFG_SCTLR_ALIGNMENT_CHECK ?= n 88 89ifeq ($(CFG_CORE_LARGE_PHYS_ADDR),y) 90$(call force,CFG_WITH_LPAE,y) 91endif 92 93# SPMC configuration "S-EL1 SPMC" where SPM Core is implemented at S-EL1, 94# that is, OP-TEE. 95ifeq ($(CFG_CORE_SEL1_SPMC),y) 96$(call force,CFG_CORE_FFA,y) 97$(call force,CFG_CORE_SEL2_SPMC,n) 98$(call force,CFG_CORE_EL3_SPMC,n) 99endif 100# SPMC configuration "S-EL2 SPMC" where SPM Core is implemented at S-EL2, 101# that is, the hypervisor sandboxing OP-TEE 102ifeq ($(CFG_CORE_SEL2_SPMC),y) 103$(call force,CFG_CORE_FFA,y) 104$(call force,CFG_CORE_SEL1_SPMC,n) 105$(call force,CFG_CORE_EL3_SPMC,n) 106endif 107# SPMC configuration "EL3 SPMC" where SPM Core is implemented at EL3, that 108# is, in TF-A 109ifeq ($(CFG_CORE_EL3_SPMC),y) 110$(call force,CFG_CORE_FFA,y) 111$(call force,CFG_CORE_SEL2_SPMC,n) 112$(call force,CFG_CORE_SEL1_SPMC,n) 113endif 114 115# Unmaps all kernel mode code except the code needed to take exceptions 116# from user space and restore kernel mode mapping again. This gives more 117# strict control over what is accessible while in user mode. 118# Addresses CVE-2017-5715 (aka Meltdown) known to affect Arm Cortex-A75 119CFG_CORE_UNMAP_CORE_AT_EL0 ?= y 120 121# Initialize PMCR.DP to 1 to prohibit cycle counting in secure state, and 122# save/restore PMCR during world switch. 123CFG_SM_NO_CYCLE_COUNTING ?= y 124 125 126# CFG_CORE_ASYNC_NOTIF_GIC_INTID is defined by the platform to some free 127# interrupt. Setting it to a non-zero number enables support for using an 128# Arm-GIC to notify normal world. This config variable should use a value 129# larger the 32 to make it of the type SPI. 130# Note that asynchronous notifactions must be enabled with 131# CFG_CORE_ASYNC_NOTIF=y for this variable to be used. 132CFG_CORE_ASYNC_NOTIF_GIC_INTID ?= 0 133 134ifeq ($(CFG_ARM32_core),y) 135# Configration directive related to ARMv7 optee boot arguments. 136# CFG_PAGEABLE_ADDR: if defined, forces pageable data physical address. 137# CFG_NS_ENTRY_ADDR: if defined, forces NS World physical entry address. 138# CFG_DT_ADDR: if defined, forces Device Tree data physical address. 139endif 140 141core-platform-cppflags += -I$(arch-dir)/include 142core-platform-subdirs += \ 143 $(addprefix $(arch-dir)/, kernel crypto mm tee) $(platform-dir) 144 145ifneq ($(CFG_WITH_ARM_TRUSTED_FW),y) 146core-platform-subdirs += $(arch-dir)/sm 147endif 148 149arm64-platform-cppflags += -DARM64=1 -D__LP64__=1 150arm32-platform-cppflags += -DARM32=1 -D__ILP32__=1 151 152platform-cflags-generic ?= -ffunction-sections -fdata-sections -pipe 153platform-aflags-generic ?= -pipe 154 155arm32-platform-aflags += -marm 156 157arm32-platform-cflags-no-hard-float ?= -mfloat-abi=soft 158arm32-platform-cflags-hard-float ?= -mfloat-abi=hard -funsafe-math-optimizations 159arm32-platform-cflags-generic-thumb ?= -mthumb \ 160 -fno-short-enums -fno-common -mno-unaligned-access 161arm32-platform-cflags-generic-arm ?= -marm -fno-omit-frame-pointer -mapcs \ 162 -fno-short-enums -fno-common -mno-unaligned-access 163arm32-platform-aflags-no-hard-float ?= 164 165arm64-platform-cflags-no-hard-float ?= -mgeneral-regs-only 166arm64-platform-cflags-hard-float ?= 167arm64-platform-cflags-generic := -mstrict-align $(call cc-option,-mno-outline-atomics,) 168 169platform-cflags-optimization ?= -O$(CFG_CC_OPT_LEVEL) 170 171ifeq ($(CFG_DEBUG_INFO),y) 172platform-cflags-debug-info ?= -g3 173platform-aflags-debug-info ?= -g 174endif 175 176core-platform-cflags += $(platform-cflags-optimization) 177core-platform-cflags += $(platform-cflags-generic) 178core-platform-cflags += $(platform-cflags-debug-info) 179 180core-platform-aflags += $(platform-aflags-generic) 181core-platform-aflags += $(platform-aflags-debug-info) 182 183ifeq ($(CFG_CORE_ASLR),y) 184core-platform-cflags += -fpie 185endif 186 187ifeq ($(CFG_CORE_BTI),y) 188bti-opt := $(call cc-option,-mbranch-protection=bti) 189ifeq (,$(bti-opt)) 190$(error -mbranch-protection=bti not supported) 191endif 192core-platform-cflags += $(bti-opt) 193endif 194 195ifeq ($(CFG_ARM64_core),y) 196core-platform-cppflags += $(arm64-platform-cppflags) 197core-platform-cflags += $(arm64-platform-cflags) 198core-platform-cflags += $(arm64-platform-cflags-generic) 199core-platform-cflags += $(arm64-platform-cflags-no-hard-float) 200core-platform-aflags += $(arm64-platform-aflags) 201else 202core-platform-cppflags += $(arm32-platform-cppflags) 203core-platform-cflags += $(arm32-platform-cflags) 204core-platform-cflags += $(arm32-platform-cflags-no-hard-float) 205ifeq ($(CFG_UNWIND),y) 206core-platform-cflags += -funwind-tables 207endif 208ifeq ($(CFG_SYSCALL_FTRACE),y) 209core-platform-cflags += $(arm32-platform-cflags-generic-arm) 210else 211core-platform-cflags += $(arm32-platform-cflags-generic-thumb) 212endif 213core-platform-aflags += $(core_arm32-platform-aflags) 214core-platform-aflags += $(arm32-platform-aflags) 215endif 216 217# Provide default supported-ta-targets if not set by the platform config 218ifeq (,$(supported-ta-targets)) 219supported-ta-targets = ta_arm32 220ifeq ($(CFG_ARM64_core),y) 221supported-ta-targets += ta_arm64 222endif 223endif 224 225ta-targets := $(if $(CFG_USER_TA_TARGETS),$(filter $(supported-ta-targets),$(CFG_USER_TA_TARGETS)),$(supported-ta-targets)) 226unsup-targets := $(filter-out $(ta-targets),$(CFG_USER_TA_TARGETS)) 227ifneq (,$(unsup-targets)) 228$(error CFG_USER_TA_TARGETS contains unsupported value(s): $(unsup-targets). Valid values: $(supported-ta-targets)) 229endif 230 231ifneq ($(filter ta_arm32,$(ta-targets)),) 232# Variables for ta-target/sm "ta_arm32" 233CFG_ARM32_ta_arm32 := y 234arch-bits-ta_arm32 := 32 235ta_arm32-platform-cppflags += $(arm32-platform-cppflags) 236ta_arm32-platform-cflags += $(arm32-platform-cflags) 237ta_arm32-platform-cflags += $(platform-cflags-optimization) 238ta_arm32-platform-cflags += $(platform-cflags-debug-info) 239ta_arm32-platform-cflags += -fpic 240 241# Thumb mode doesn't support function graph tracing due to missing 242# frame pointer support required to trace function call chain. So 243# rather compile in ARM mode if function tracing is enabled. 244ifeq ($(CFG_FTRACE_SUPPORT),y) 245ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-arm) 246else 247ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-thumb) 248endif 249 250ifeq ($(arm32-platform-hard-float-enabled),y) 251ta_arm32-platform-cflags += $(arm32-platform-cflags-hard-float) 252else 253ta_arm32-platform-cflags += $(arm32-platform-cflags-no-hard-float) 254endif 255ifeq ($(CFG_UNWIND),y) 256ta_arm32-platform-cflags += -funwind-tables 257endif 258ta_arm32-platform-aflags += $(platform-aflags-generic) 259ta_arm32-platform-aflags += $(platform-aflags-debug-info) 260ta_arm32-platform-aflags += $(arm32-platform-aflags) 261 262ta_arm32-platform-cxxflags += -fpic 263ta_arm32-platform-cxxflags += $(arm32-platform-cxxflags) 264ta_arm32-platform-cxxflags += $(platform-cflags-optimization) 265ta_arm32-platform-cxxflags += $(platform-cflags-debug-info) 266 267ifeq ($(arm32-platform-hard-float-enabled),y) 268ta_arm32-platform-cxxflags += $(arm32-platform-cflags-hard-float) 269else 270ta_arm32-platform-cxxflags += $(arm32-platform-cflags-no-hard-float) 271endif 272 273ta-mk-file-export-vars-ta_arm32 += CFG_ARM32_ta_arm32 274ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cppflags 275ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cflags 276ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-aflags 277ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cxxflags 278 279ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE ?= arm-linux-gnueabihf-_nl_ 280ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE32 ?= $$(CROSS_COMPILE)_nl_ 281ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE_ta_arm32 ?= $$(CROSS_COMPILE32)_nl_ 282ta-mk-file-export-add-ta_arm32 += COMPILER ?= gcc_nl_ 283ta-mk-file-export-add-ta_arm32 += COMPILER_ta_arm32 ?= $$(COMPILER)_nl_ 284ta-mk-file-export-add-ta_arm32 += PYTHON3 ?= python3_nl_ 285endif 286 287ifneq ($(filter ta_arm64,$(ta-targets)),) 288# Variables for ta-target/sm "ta_arm64" 289CFG_ARM64_ta_arm64 := y 290arch-bits-ta_arm64 := 64 291ta_arm64-platform-cppflags += $(arm64-platform-cppflags) 292ta_arm64-platform-cflags += $(arm64-platform-cflags) 293ta_arm64-platform-cflags += $(platform-cflags-optimization) 294ta_arm64-platform-cflags += $(platform-cflags-debug-info) 295ta_arm64-platform-cflags += -fpic 296ta_arm64-platform-cflags += $(arm64-platform-cflags-generic) 297ifeq ($(arm64-platform-hard-float-enabled),y) 298ta_arm64-platform-cflags += $(arm64-platform-cflags-hard-float) 299else 300ta_arm64-platform-cflags += $(arm64-platform-cflags-no-hard-float) 301endif 302ta_arm64-platform-aflags += $(platform-aflags-generic) 303ta_arm64-platform-aflags += $(platform-aflags-debug-info) 304ta_arm64-platform-aflags += $(arm64-platform-aflags) 305 306ta_arm64-platform-cxxflags += -fpic 307ta_arm64-platform-cxxflags += $(platform-cflags-optimization) 308ta_arm64-platform-cxxflags += $(platform-cflags-debug-info) 309 310ifeq ($(CFG_TA_PAUTH),y) 311bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf) 312endif 313 314ifeq ($(CFG_TA_BTI),y) 315bp-ta-opt := $(call cc-option,-mbranch-protection=bti) 316endif 317 318ifeq (y-y,$(CFG_TA_PAUTH)-$(CFG_TA_BTI)) 319bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf+bti) 320endif 321 322ifeq (y,$(filter $(CFG_TA_BTI) $(CFG_TA_PAUTH),y)) 323ifeq (,$(bp-ta-opt)) 324$(error -mbranch-protection not supported) 325endif 326ta_arm64-platform-cflags += $(bp-ta-opt) 327endif 328 329ta-mk-file-export-vars-ta_arm64 += CFG_ARM64_ta_arm64 330ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cppflags 331ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cflags 332ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-aflags 333ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cxxflags 334 335ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE64 ?= $$(CROSS_COMPILE)_nl_ 336ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE_ta_arm64 ?= $$(CROSS_COMPILE64)_nl_ 337ta-mk-file-export-add-ta_arm64 += COMPILER ?= gcc_nl_ 338ta-mk-file-export-add-ta_arm64 += COMPILER_ta_arm64 ?= $$(COMPILER)_nl_ 339ta-mk-file-export-add-ta_arm64 += PYTHON3 ?= python3_nl_ 340endif 341 342# Set cross compiler prefix for each TA target 343$(foreach sm, $(ta-targets), $(eval CROSS_COMPILE_$(sm) ?= $(CROSS_COMPILE$(arch-bits-$(sm))))) 344 345arm32-sysreg-txt = core/arch/arm/kernel/arm32_sysreg.txt 346arm32-sysregs-$(arm32-sysreg-txt)-h := arm32_sysreg.h 347arm32-sysregs-$(arm32-sysreg-txt)-s := arm32_sysreg.S 348arm32-sysregs += $(arm32-sysreg-txt) 349 350ifeq ($(CFG_ARM_GICV3),y) 351arm32-gicv3-sysreg-txt = core/arch/arm/kernel/arm32_gicv3_sysreg.txt 352arm32-sysregs-$(arm32-gicv3-sysreg-txt)-h := arm32_gicv3_sysreg.h 353arm32-sysregs-$(arm32-gicv3-sysreg-txt)-s := arm32_gicv3_sysreg.S 354arm32-sysregs += $(arm32-gicv3-sysreg-txt) 355endif 356 357arm32-sysregs-out := $(out-dir)/$(sm)/include/generated 358 359define process-arm32-sysreg 360FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 361cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 362 363$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h): $(1) scripts/arm32_sysreg.py 364 @$(cmd-echo-silent) ' GEN $$@' 365 $(q)mkdir -p $$(dir $$@) 366 $(q)scripts/arm32_sysreg.py --guard __$$(arm32-sysregs-$(1)-h) \ 367 < $$< > $$@ 368 369FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 370cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 371 372$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s): $(1) scripts/arm32_sysreg.py 373 @$(cmd-echo-silent) ' GEN $$@' 374 $(q)mkdir -p $$(dir $$@) 375 $(q)scripts/arm32_sysreg.py --s_file < $$< > $$@ 376endef #process-arm32-sysreg 377 378$(foreach sr, $(arm32-sysregs), $(eval $(call process-arm32-sysreg,$(sr)))) 379