1# Setup compiler for the core module 2ifeq ($(CFG_ARM64_core),y) 3arch-bits-core := 64 4else 5arch-bits-core := 32 6endif 7CROSS_COMPILE_core := $(CROSS_COMPILE$(arch-bits-core)) 8COMPILER_core := $(COMPILER) 9include mk/$(COMPILER_core).mk 10 11# Defines the cc-option macro using the compiler set for the core module 12include mk/cc-option.mk 13 14# Size of emulated TrustZone protected SRAM, 448 kB. 15# Only applicable when paging is enabled. 16CFG_CORE_TZSRAM_EMUL_SIZE ?= 458752 17 18ifneq ($(CFG_LPAE_ADDR_SPACE_SIZE),) 19$(warning Error: CFG_LPAE_ADDR_SPACE_SIZE is not supported any longer) 20$(error Error: Please use CFG_LPAE_ADDR_SPACE_BITS instead) 21endif 22 23CFG_LPAE_ADDR_SPACE_BITS ?= 32 24 25CFG_MMAP_REGIONS ?= 13 26CFG_RESERVED_VASPACE_SIZE ?= (1024 * 1024 * 10) 27 28ifeq ($(CFG_ARM64_core),y) 29CFG_KERN_LINKER_FORMAT ?= elf64-littleaarch64 30CFG_KERN_LINKER_ARCH ?= aarch64 31# TCR_EL1.IPS needs to be initialized according to the largest physical 32# address that we need to map. 33# Physical address size 34# 32 bits, 4GB. 35# 36 bits, 64GB. 36# (etc.) 37CFG_CORE_ARM64_PA_BITS ?= 32 38else 39ifeq ($(CFG_ARM32_core),y) 40CFG_KERN_LINKER_FORMAT ?= elf32-littlearm 41CFG_KERN_LINKER_ARCH ?= arm 42else 43$(error Error: CFG_ARM64_core or CFG_ARM32_core should be defined) 44endif 45endif 46 47ifeq ($(CFG_TA_FLOAT_SUPPORT),y) 48# Use hard-float for floating point support in user TAs instead of 49# soft-float 50CFG_WITH_VFP ?= y 51ifeq ($(CFG_ARM64_core),y) 52# AArch64 has no fallback to soft-float 53$(call force,CFG_WITH_VFP,y) 54endif 55ifeq ($(CFG_WITH_VFP),y) 56arm64-platform-hard-float-enabled := y 57ifneq ($(CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT),y) 58arm32-platform-hard-float-enabled := y 59endif 60endif 61endif 62 63# Adds protection against CVE-2017-5715 also know as Spectre 64# (https://spectreattack.com) 65# See also https://developer.arm.com/-/media/Files/pdf/Cache_Speculation_Side-channels.pdf 66# Variant 2 67CFG_CORE_WORKAROUND_SPECTRE_BP ?= y 68# Same as CFG_CORE_WORKAROUND_SPECTRE_BP but targeting exceptions from 69# secure EL0 instead of non-secure world, including mitigation for 70# CVE-2022-23960. 71CFG_CORE_WORKAROUND_SPECTRE_BP_SEC ?= $(CFG_CORE_WORKAROUND_SPECTRE_BP) 72 73# Adds protection against a tool like Cachegrab 74# (https://github.com/nccgroup/cachegrab), which uses non-secure interrupts 75# to prime and later analyze the L1D, L1I and BTB caches to gain 76# information from secure world execution. 77CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME ?= y 78ifeq ($(CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME),y) 79$(call force,CFG_CORE_WORKAROUND_SPECTRE_BP,y,Required by CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME) 80endif 81 82CFG_CORE_RWDATA_NOEXEC ?= y 83CFG_CORE_RODATA_NOEXEC ?= n 84ifeq ($(CFG_CORE_RODATA_NOEXEC),y) 85$(call force,CFG_CORE_RWDATA_NOEXEC,y) 86endif 87# 'y' to set the Alignment Check Enable bit in SCTLR/SCTLR_EL1, 'n' to clear it 88CFG_SCTLR_ALIGNMENT_CHECK ?= n 89 90ifeq ($(CFG_CORE_LARGE_PHYS_ADDR),y) 91$(call force,CFG_WITH_LPAE,y) 92endif 93 94# SPMC configuration "S-EL1 SPMC" where SPM Core is implemented at S-EL1, 95# that is, OP-TEE. 96ifeq ($(CFG_CORE_SEL1_SPMC),y) 97$(call force,CFG_CORE_FFA,y) 98$(call force,CFG_CORE_SEL2_SPMC,n) 99$(call force,CFG_CORE_EL3_SPMC,n) 100endif 101# SPMC configuration "S-EL2 SPMC" where SPM Core is implemented at S-EL2, 102# that is, the hypervisor sandboxing OP-TEE 103ifeq ($(CFG_CORE_SEL2_SPMC),y) 104$(call force,CFG_CORE_FFA,y) 105$(call force,CFG_CORE_SEL1_SPMC,n) 106$(call force,CFG_CORE_EL3_SPMC,n) 107endif 108# SPMC configuration "EL3 SPMC" where SPM Core is implemented at EL3, that 109# is, in TF-A 110ifeq ($(CFG_CORE_EL3_SPMC),y) 111$(call force,CFG_CORE_FFA,y) 112$(call force,CFG_CORE_SEL2_SPMC,n) 113$(call force,CFG_CORE_SEL1_SPMC,n) 114endif 115 116# Unmaps all kernel mode code except the code needed to take exceptions 117# from user space and restore kernel mode mapping again. This gives more 118# strict control over what is accessible while in user mode. 119# Addresses CVE-2017-5715 (aka Meltdown) known to affect Arm Cortex-A75 120CFG_CORE_UNMAP_CORE_AT_EL0 ?= y 121 122# Initialize PMCR.DP to 1 to prohibit cycle counting in secure state, and 123# save/restore PMCR during world switch. 124CFG_SM_NO_CYCLE_COUNTING ?= y 125 126 127# CFG_CORE_ASYNC_NOTIF_GIC_INTID is defined by the platform to some free 128# interrupt. Setting it to a non-zero number enables support for using an 129# Arm-GIC to notify normal world. This config variable should use a value 130# larger the 32 to make it of the type SPI. 131# Note that asynchronous notifactions must be enabled with 132# CFG_CORE_ASYNC_NOTIF=y for this variable to be used. 133CFG_CORE_ASYNC_NOTIF_GIC_INTID ?= 0 134 135ifeq ($(CFG_ARM32_core),y) 136# Configration directive related to ARMv7 optee boot arguments. 137# CFG_PAGEABLE_ADDR: if defined, forces pageable data physical address. 138# CFG_NS_ENTRY_ADDR: if defined, forces NS World physical entry address. 139# CFG_DT_ADDR: if defined, forces Device Tree data physical address. 140endif 141 142core-platform-cppflags += -I$(arch-dir)/include 143core-platform-subdirs += \ 144 $(addprefix $(arch-dir)/, kernel crypto mm tee) $(platform-dir) 145 146ifneq ($(CFG_WITH_ARM_TRUSTED_FW),y) 147core-platform-subdirs += $(arch-dir)/sm 148endif 149 150arm64-platform-cppflags += -DARM64=1 -D__LP64__=1 151arm32-platform-cppflags += -DARM32=1 -D__ILP32__=1 152 153platform-cflags-generic ?= -ffunction-sections -fdata-sections -pipe 154platform-aflags-generic ?= -pipe 155 156arm32-platform-aflags += -marm 157 158arm32-platform-cflags-no-hard-float ?= -mfloat-abi=soft 159arm32-platform-cflags-hard-float ?= -mfloat-abi=hard -funsafe-math-optimizations 160arm32-platform-cflags-generic-thumb ?= -mthumb \ 161 -fno-short-enums -fno-common -mno-unaligned-access 162arm32-platform-cflags-generic-arm ?= -marm -fno-omit-frame-pointer -mapcs \ 163 -fno-short-enums -fno-common -mno-unaligned-access 164arm32-platform-aflags-no-hard-float ?= 165 166arm64-platform-cflags-no-hard-float ?= -mgeneral-regs-only 167arm64-platform-cflags-hard-float ?= 168arm64-platform-cflags-generic := -mstrict-align $(call cc-option,-mno-outline-atomics,) 169 170platform-cflags-optimization ?= -O$(CFG_CC_OPT_LEVEL) 171 172ifeq ($(CFG_DEBUG_INFO),y) 173platform-cflags-debug-info ?= -g3 174platform-aflags-debug-info ?= -g 175endif 176 177core-platform-cflags += $(platform-cflags-optimization) 178core-platform-cflags += $(platform-cflags-generic) 179core-platform-cflags += $(platform-cflags-debug-info) 180 181core-platform-aflags += $(platform-aflags-generic) 182core-platform-aflags += $(platform-aflags-debug-info) 183 184ifeq ($(CFG_CORE_ASLR),y) 185core-platform-cflags += -fpie 186endif 187 188ifeq ($(CFG_CORE_BTI),y) 189bti-opt := $(call cc-option,-mbranch-protection=bti) 190ifeq (,$(bti-opt)) 191$(error -mbranch-protection=bti not supported) 192endif 193core-platform-cflags += $(bti-opt) 194endif 195 196ifeq ($(CFG_ARM64_core),y) 197core-platform-cppflags += $(arm64-platform-cppflags) 198core-platform-cflags += $(arm64-platform-cflags) 199core-platform-cflags += $(arm64-platform-cflags-generic) 200core-platform-cflags += $(arm64-platform-cflags-no-hard-float) 201core-platform-aflags += $(arm64-platform-aflags) 202else 203core-platform-cppflags += $(arm32-platform-cppflags) 204core-platform-cflags += $(arm32-platform-cflags) 205core-platform-cflags += $(arm32-platform-cflags-no-hard-float) 206ifeq ($(CFG_UNWIND),y) 207core-platform-cflags += -funwind-tables 208endif 209ifeq ($(CFG_SYSCALL_FTRACE),y) 210core-platform-cflags += $(arm32-platform-cflags-generic-arm) 211else 212core-platform-cflags += $(arm32-platform-cflags-generic-thumb) 213endif 214core-platform-aflags += $(core_arm32-platform-aflags) 215core-platform-aflags += $(arm32-platform-aflags) 216endif 217 218# Provide default supported-ta-targets if not set by the platform config 219ifeq (,$(supported-ta-targets)) 220supported-ta-targets = ta_arm32 221ifeq ($(CFG_ARM64_core),y) 222supported-ta-targets += ta_arm64 223endif 224endif 225 226ta-targets := $(if $(CFG_USER_TA_TARGETS),$(filter $(supported-ta-targets),$(CFG_USER_TA_TARGETS)),$(supported-ta-targets)) 227unsup-targets := $(filter-out $(ta-targets),$(CFG_USER_TA_TARGETS)) 228ifneq (,$(unsup-targets)) 229$(error CFG_USER_TA_TARGETS contains unsupported value(s): $(unsup-targets). Valid values: $(supported-ta-targets)) 230endif 231 232ifneq ($(filter ta_arm32,$(ta-targets)),) 233# Variables for ta-target/sm "ta_arm32" 234CFG_ARM32_ta_arm32 := y 235arch-bits-ta_arm32 := 32 236ta_arm32-platform-cppflags += $(arm32-platform-cppflags) 237ta_arm32-platform-cflags += $(arm32-platform-cflags) 238ta_arm32-platform-cflags += $(platform-cflags-optimization) 239ta_arm32-platform-cflags += $(platform-cflags-debug-info) 240ta_arm32-platform-cflags += -fpic 241 242# Thumb mode doesn't support function graph tracing due to missing 243# frame pointer support required to trace function call chain. So 244# rather compile in ARM mode if function tracing is enabled. 245ifeq ($(CFG_FTRACE_SUPPORT),y) 246ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-arm) 247else 248ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-thumb) 249endif 250 251ifeq ($(arm32-platform-hard-float-enabled),y) 252ta_arm32-platform-cflags += $(arm32-platform-cflags-hard-float) 253else 254ta_arm32-platform-cflags += $(arm32-platform-cflags-no-hard-float) 255endif 256ifeq ($(CFG_UNWIND),y) 257ta_arm32-platform-cflags += -funwind-tables 258endif 259ta_arm32-platform-aflags += $(platform-aflags-generic) 260ta_arm32-platform-aflags += $(platform-aflags-debug-info) 261ta_arm32-platform-aflags += $(arm32-platform-aflags) 262 263ta_arm32-platform-cxxflags += -fpic 264ta_arm32-platform-cxxflags += $(arm32-platform-cxxflags) 265ta_arm32-platform-cxxflags += $(platform-cflags-optimization) 266ta_arm32-platform-cxxflags += $(platform-cflags-debug-info) 267 268ifeq ($(arm32-platform-hard-float-enabled),y) 269ta_arm32-platform-cxxflags += $(arm32-platform-cflags-hard-float) 270else 271ta_arm32-platform-cxxflags += $(arm32-platform-cflags-no-hard-float) 272endif 273 274ta-mk-file-export-vars-ta_arm32 += CFG_ARM32_ta_arm32 275ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cppflags 276ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cflags 277ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-aflags 278ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cxxflags 279 280ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE ?= arm-linux-gnueabihf-_nl_ 281ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE32 ?= $$(CROSS_COMPILE)_nl_ 282ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE_ta_arm32 ?= $$(CROSS_COMPILE32)_nl_ 283ta-mk-file-export-add-ta_arm32 += COMPILER ?= gcc_nl_ 284ta-mk-file-export-add-ta_arm32 += COMPILER_ta_arm32 ?= $$(COMPILER)_nl_ 285ta-mk-file-export-add-ta_arm32 += PYTHON3 ?= python3_nl_ 286endif 287 288ifneq ($(filter ta_arm64,$(ta-targets)),) 289# Variables for ta-target/sm "ta_arm64" 290CFG_ARM64_ta_arm64 := y 291arch-bits-ta_arm64 := 64 292ta_arm64-platform-cppflags += $(arm64-platform-cppflags) 293ta_arm64-platform-cflags += $(arm64-platform-cflags) 294ta_arm64-platform-cflags += $(platform-cflags-optimization) 295ta_arm64-platform-cflags += $(platform-cflags-debug-info) 296ta_arm64-platform-cflags += -fpic 297ta_arm64-platform-cflags += $(arm64-platform-cflags-generic) 298ifeq ($(arm64-platform-hard-float-enabled),y) 299ta_arm64-platform-cflags += $(arm64-platform-cflags-hard-float) 300else 301ta_arm64-platform-cflags += $(arm64-platform-cflags-no-hard-float) 302endif 303ta_arm64-platform-aflags += $(platform-aflags-generic) 304ta_arm64-platform-aflags += $(platform-aflags-debug-info) 305ta_arm64-platform-aflags += $(arm64-platform-aflags) 306 307ta_arm64-platform-cxxflags += -fpic 308ta_arm64-platform-cxxflags += $(platform-cflags-optimization) 309ta_arm64-platform-cxxflags += $(platform-cflags-debug-info) 310 311ifeq ($(CFG_TA_PAUTH),y) 312bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf) 313endif 314 315ifeq ($(CFG_TA_BTI),y) 316bp-ta-opt := $(call cc-option,-mbranch-protection=bti) 317endif 318 319ifeq (y-y,$(CFG_TA_PAUTH)-$(CFG_TA_BTI)) 320bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf+bti) 321endif 322 323ifeq (y,$(filter $(CFG_TA_BTI) $(CFG_TA_PAUTH),y)) 324ifeq (,$(bp-ta-opt)) 325$(error -mbranch-protection not supported) 326endif 327ta_arm64-platform-cflags += $(bp-ta-opt) 328endif 329 330ta-mk-file-export-vars-ta_arm64 += CFG_ARM64_ta_arm64 331ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cppflags 332ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cflags 333ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-aflags 334ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cxxflags 335 336ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE64 ?= $$(CROSS_COMPILE)_nl_ 337ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE_ta_arm64 ?= $$(CROSS_COMPILE64)_nl_ 338ta-mk-file-export-add-ta_arm64 += COMPILER ?= gcc_nl_ 339ta-mk-file-export-add-ta_arm64 += COMPILER_ta_arm64 ?= $$(COMPILER)_nl_ 340ta-mk-file-export-add-ta_arm64 += PYTHON3 ?= python3_nl_ 341endif 342 343# Set cross compiler prefix for each TA target 344$(foreach sm, $(ta-targets), $(eval CROSS_COMPILE_$(sm) ?= $(CROSS_COMPILE$(arch-bits-$(sm))))) 345 346arm32-sysreg-txt = core/arch/arm/kernel/arm32_sysreg.txt 347arm32-sysregs-$(arm32-sysreg-txt)-h := arm32_sysreg.h 348arm32-sysregs-$(arm32-sysreg-txt)-s := arm32_sysreg.S 349arm32-sysregs += $(arm32-sysreg-txt) 350 351ifeq ($(CFG_ARM_GICV3),y) 352arm32-gicv3-sysreg-txt = core/arch/arm/kernel/arm32_gicv3_sysreg.txt 353arm32-sysregs-$(arm32-gicv3-sysreg-txt)-h := arm32_gicv3_sysreg.h 354arm32-sysregs-$(arm32-gicv3-sysreg-txt)-s := arm32_gicv3_sysreg.S 355arm32-sysregs += $(arm32-gicv3-sysreg-txt) 356endif 357 358arm32-sysregs-out := $(out-dir)/$(sm)/include/generated 359 360define process-arm32-sysreg 361FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 362cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 363 364$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h): $(1) scripts/arm32_sysreg.py 365 @$(cmd-echo-silent) ' GEN $$@' 366 $(q)mkdir -p $$(dir $$@) 367 $(q)scripts/arm32_sysreg.py --guard __$$(arm32-sysregs-$(1)-h) \ 368 < $$< > $$@ 369 370FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 371cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 372 373$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s): $(1) scripts/arm32_sysreg.py 374 @$(cmd-echo-silent) ' GEN $$@' 375 $(q)mkdir -p $$(dir $$@) 376 $(q)scripts/arm32_sysreg.py --s_file < $$< > $$@ 377endef #process-arm32-sysreg 378 379$(foreach sr, $(arm32-sysregs), $(eval $(call process-arm32-sysreg,$(sr)))) 380