1# Setup compiler for the core module 2ifeq ($(CFG_ARM64_core),y) 3arch-bits-core := 64 4else 5arch-bits-core := 32 6endif 7CROSS_COMPILE_core := $(CROSS_COMPILE$(arch-bits-core)) 8COMPILER_core := $(COMPILER) 9include mk/$(COMPILER_core).mk 10 11# Defines the cc-option macro using the compiler set for the core module 12include mk/cc-option.mk 13 14# Size of emulated TrustZone protected SRAM, 448 kB. 15# Only applicable when paging is enabled. 16CFG_CORE_TZSRAM_EMUL_SIZE ?= 458752 17 18ifneq ($(CFG_LPAE_ADDR_SPACE_SIZE),) 19$(warning Error: CFG_LPAE_ADDR_SPACE_SIZE is not supported any longer) 20$(error Error: Please use CFG_LPAE_ADDR_SPACE_BITS instead) 21endif 22 23CFG_LPAE_ADDR_SPACE_BITS ?= 32 24 25CFG_MMAP_REGIONS ?= 13 26CFG_RESERVED_VASPACE_SIZE ?= (1024 * 1024 * 10) 27 28ifeq ($(CFG_ARM64_core),y) 29ifeq ($(CFG_ARM32_core),y) 30$(error CFG_ARM64_core and CFG_ARM32_core cannot be both 'y') 31endif 32CFG_KERN_LINKER_FORMAT ?= elf64-littleaarch64 33CFG_KERN_LINKER_ARCH ?= aarch64 34# TCR_EL1.IPS needs to be initialized according to the largest physical 35# address that we need to map. 36# Physical address size 37# 32 bits, 4GB. 38# 36 bits, 64GB. 39# (etc.) 40CFG_CORE_ARM64_PA_BITS ?= 32 41$(call force,CFG_WITH_LPAE,y) 42else 43$(call force,CFG_ARM32_core,y) 44CFG_KERN_LINKER_FORMAT ?= elf32-littlearm 45CFG_KERN_LINKER_ARCH ?= arm 46endif 47 48ifeq ($(CFG_TA_FLOAT_SUPPORT),y) 49# Use hard-float for floating point support in user TAs instead of 50# soft-float 51CFG_WITH_VFP ?= y 52ifeq ($(CFG_ARM64_core),y) 53# AArch64 has no fallback to soft-float 54$(call force,CFG_WITH_VFP,y) 55endif 56ifeq ($(CFG_WITH_VFP),y) 57arm64-platform-hard-float-enabled := y 58ifneq ($(CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT),y) 59arm32-platform-hard-float-enabled := y 60endif 61endif 62endif 63 64# Adds protection against CVE-2017-5715 also know as Spectre 65# (https://spectreattack.com) 66# See also https://developer.arm.com/-/media/Files/pdf/Cache_Speculation_Side-channels.pdf 67# Variant 2 68CFG_CORE_WORKAROUND_SPECTRE_BP ?= y 69# Same as CFG_CORE_WORKAROUND_SPECTRE_BP but targeting exceptions from 70# secure EL0 instead of non-secure world, including mitigation for 71# CVE-2022-23960. 72CFG_CORE_WORKAROUND_SPECTRE_BP_SEC ?= $(CFG_CORE_WORKAROUND_SPECTRE_BP) 73 74# Adds protection against a tool like Cachegrab 75# (https://github.com/nccgroup/cachegrab), which uses non-secure interrupts 76# to prime and later analyze the L1D, L1I and BTB caches to gain 77# information from secure world execution. 78CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME ?= y 79ifeq ($(CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME),y) 80$(call force,CFG_CORE_WORKAROUND_SPECTRE_BP,y,Required by CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME) 81endif 82 83# Adds workarounds against if ARM core is configured with Non-maskable FIQ 84# (NMFI) support. This is indicated by SCTLR.NMFI being true. NMFI cannot be 85# disabled by software and as it affects atomic context end result will be 86# prohibiting FIQ signal usage in OP-TEE and applying some tweaks to make sure 87# FIQ is enabled in critical places. 88CFG_CORE_WORKAROUND_ARM_NMFI ?= n 89 90CFG_CORE_RWDATA_NOEXEC ?= y 91CFG_CORE_RODATA_NOEXEC ?= n 92ifeq ($(CFG_CORE_RODATA_NOEXEC),y) 93$(call force,CFG_CORE_RWDATA_NOEXEC,y) 94endif 95# 'y' to set the Alignment Check Enable bit in SCTLR/SCTLR_EL1, 'n' to clear it 96CFG_SCTLR_ALIGNMENT_CHECK ?= n 97 98ifeq ($(CFG_CORE_LARGE_PHYS_ADDR),y) 99$(call force,CFG_WITH_LPAE,y) 100endif 101 102# SPMC configuration "S-EL1 SPMC" where SPM Core is implemented at S-EL1, 103# that is, OP-TEE. 104ifeq ($(CFG_CORE_SEL1_SPMC),y) 105$(call force,CFG_CORE_FFA,y) 106$(call force,CFG_CORE_SEL2_SPMC,n) 107$(call force,CFG_CORE_EL3_SPMC,n) 108endif 109# SPMC configuration "S-EL2 SPMC" where SPM Core is implemented at S-EL2, 110# that is, the hypervisor sandboxing OP-TEE 111ifeq ($(CFG_CORE_SEL2_SPMC),y) 112$(call force,CFG_CORE_FFA,y) 113$(call force,CFG_CORE_SEL1_SPMC,n) 114$(call force,CFG_CORE_EL3_SPMC,n) 115CFG_CORE_HAFNIUM_INTC ?= y 116# Enable support in OP-TEE to relocate itself to allow it to run from a 117# physical address that differs from the link address 118CFG_CORE_PHYS_RELOCATABLE ?= y 119endif 120# SPMC configuration "EL3 SPMC" where SPM Core is implemented at EL3, that 121# is, in TF-A 122ifeq ($(CFG_CORE_EL3_SPMC),y) 123$(call force,CFG_CORE_FFA,y) 124$(call force,CFG_CORE_SEL2_SPMC,n) 125$(call force,CFG_CORE_SEL1_SPMC,n) 126endif 127 128ifeq ($(CFG_CORE_FFA),y) 129ifneq ($(CFG_DT),y) 130$(error CFG_CORE_FFA depends on CFG_DT) 131endif 132endif 133 134ifeq ($(CFG_CORE_PHYS_RELOCATABLE)-$(CFG_WITH_PAGER),y-y) 135$(error CFG_CORE_PHYS_RELOCATABLE and CFG_WITH_PAGER are not compatible) 136endif 137ifeq ($(CFG_CORE_PHYS_RELOCATABLE),y) 138ifneq ($(CFG_CORE_SEL2_SPMC),y) 139$(error CFG_CORE_PHYS_RELOCATABLE depends on CFG_CORE_SEL2_SPMC) 140endif 141endif 142 143ifeq ($(CFG_CORE_FFA)-$(CFG_WITH_PAGER),y-y) 144$(error CFG_CORE_FFA and CFG_WITH_PAGER are not compatible) 145endif 146ifeq ($(CFG_GIC),y) 147ifeq ($(CFG_ARM_GICV3),y) 148$(call force,CFG_CORE_IRQ_IS_NATIVE_INTR,y) 149else 150$(call force,CFG_CORE_IRQ_IS_NATIVE_INTR,n) 151endif 152endif 153 154CFG_CORE_HAFNIUM_INTC ?= n 155ifeq ($(CFG_CORE_HAFNIUM_INTC),y) 156$(call force,CFG_CORE_IRQ_IS_NATIVE_INTR,y) 157endif 158 159# Selects if IRQ is used to signal native interrupt 160# if CFG_CORE_IRQ_IS_NATIVE_INTR == y: 161# IRQ signals a native interrupt pending 162# FIQ signals a foreign non-secure interrupt or a managed exit pending 163# else: (vice versa) 164# IRQ signals a foreign non-secure interrupt or a managed exit pending 165# FIQ signals a native interrupt pending 166CFG_CORE_IRQ_IS_NATIVE_INTR ?= n 167 168# Unmaps all kernel mode code except the code needed to take exceptions 169# from user space and restore kernel mode mapping again. This gives more 170# strict control over what is accessible while in user mode. 171# Addresses CVE-2017-5715 (aka Meltdown) known to affect Arm Cortex-A75 172CFG_CORE_UNMAP_CORE_AT_EL0 ?= y 173 174# Initialize PMCR.DP to 1 to prohibit cycle counting in secure state, and 175# save/restore PMCR during world switch. 176CFG_SM_NO_CYCLE_COUNTING ?= y 177 178 179# CFG_CORE_ASYNC_NOTIF_GIC_INTID is defined by the platform to some free 180# interrupt. Setting it to a non-zero number enables support for using an 181# Arm-GIC to notify normal world. This config variable should use a value 182# larger the 32 to make it of the type SPI. 183# Note that asynchronous notifactions must be enabled with 184# CFG_CORE_ASYNC_NOTIF=y for this variable to be used. 185CFG_CORE_ASYNC_NOTIF_GIC_INTID ?= 0 186 187ifeq ($(CFG_ARM32_core),y) 188# Configration directive related to ARMv7 optee boot arguments. 189# CFG_PAGEABLE_ADDR: if defined, forces pageable data physical address. 190# CFG_NS_ENTRY_ADDR: if defined, forces NS World physical entry address. 191# CFG_DT_ADDR: if defined, forces Device Tree data physical address. 192endif 193 194# CFG_MAX_CACHE_LINE_SHIFT is used to define platform specific maximum cache 195# line size in address lines. This must cover all inner and outer cache levels. 196# When data is aligned with this and cache operations are performed then those 197# only affect correct data. 198# 199# Default value (6 lines or 64 bytes) should cover most architectures, override 200# this in platform config if different. 201CFG_MAX_CACHE_LINE_SHIFT ?= 6 202 203core-platform-cppflags += -I$(arch-dir)/include 204core-platform-subdirs += \ 205 $(addprefix $(arch-dir)/, kernel crypto mm tee) $(platform-dir) 206 207ifneq ($(CFG_WITH_ARM_TRUSTED_FW),y) 208core-platform-subdirs += $(arch-dir)/sm 209endif 210 211arm64-platform-cppflags += -DARM64=1 -D__LP64__=1 212arm32-platform-cppflags += -DARM32=1 -D__ILP32__=1 213 214platform-cflags-generic ?= -ffunction-sections -fdata-sections -pipe 215platform-aflags-generic ?= -pipe 216 217arm32-platform-aflags += -marm 218 219arm32-platform-cflags-no-hard-float ?= -mfloat-abi=soft 220arm32-platform-cflags-hard-float ?= -mfloat-abi=hard -funsafe-math-optimizations 221arm32-platform-cflags-generic-thumb ?= -mthumb \ 222 -fno-short-enums -fno-common -mno-unaligned-access 223arm32-platform-cflags-generic-arm ?= -marm -fno-omit-frame-pointer -mapcs \ 224 -fno-short-enums -fno-common -mno-unaligned-access 225arm32-platform-aflags-no-hard-float ?= 226 227arm64-platform-cflags-no-hard-float ?= -mgeneral-regs-only 228arm64-platform-cflags-hard-float ?= 229arm64-platform-cflags-generic := -mstrict-align $(call cc-option,-mno-outline-atomics,) 230 231ifeq ($(CFG_MEMTAG),y) 232arm64-platform-cflags += -march=armv8.5-a+memtag 233arm64-platform-aflags += -march=armv8.5-a+memtag 234endif 235 236platform-cflags-optimization ?= -O$(CFG_CC_OPT_LEVEL) 237 238ifeq ($(CFG_DEBUG_INFO),y) 239platform-cflags-debug-info ?= -g3 240platform-aflags-debug-info ?= -g 241endif 242 243core-platform-cflags += $(platform-cflags-optimization) 244core-platform-cflags += $(platform-cflags-generic) 245core-platform-cflags += $(platform-cflags-debug-info) 246 247core-platform-aflags += $(platform-aflags-generic) 248core-platform-aflags += $(platform-aflags-debug-info) 249 250ifeq ($(call cfg-one-enabled, CFG_CORE_ASLR CFG_CORE_PHYS_RELOCATABLE),y) 251core-platform-cflags += -fpie 252endif 253 254ifeq ($(CFG_CORE_PAUTH),y) 255bp-core-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf) 256endif 257 258ifeq ($(CFG_CORE_BTI),y) 259bp-core-opt := $(call cc-option,-mbranch-protection=bti) 260endif 261 262ifeq (y-y,$(CFG_CORE_PAUTH)-$(CFG_CORE_BTI)) 263bp-core-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf+bti) 264endif 265 266ifeq (y,$(filter $(CFG_CORE_BTI) $(CFG_CORE_PAUTH),y)) 267ifeq (,$(bp-core-opt)) 268$(error -mbranch-protection not supported) 269endif 270core-platform-cflags += $(bp-core-opt) 271endif 272 273ifeq ($(CFG_ARM64_core),y) 274core-platform-cppflags += $(arm64-platform-cppflags) 275core-platform-cflags += $(arm64-platform-cflags) 276core-platform-cflags += $(arm64-platform-cflags-generic) 277core-platform-cflags += $(arm64-platform-cflags-no-hard-float) 278core-platform-aflags += $(arm64-platform-aflags) 279else 280core-platform-cppflags += $(arm32-platform-cppflags) 281core-platform-cflags += $(arm32-platform-cflags) 282core-platform-cflags += $(arm32-platform-cflags-no-hard-float) 283ifeq ($(CFG_UNWIND),y) 284core-platform-cflags += -funwind-tables 285endif 286ifeq ($(CFG_SYSCALL_FTRACE),y) 287core-platform-cflags += $(arm32-platform-cflags-generic-arm) 288else 289core-platform-cflags += $(arm32-platform-cflags-generic-thumb) 290endif 291core-platform-aflags += $(core_arm32-platform-aflags) 292core-platform-aflags += $(arm32-platform-aflags) 293endif 294 295# Provide default supported-ta-targets if not set by the platform config 296ifeq (,$(supported-ta-targets)) 297supported-ta-targets = ta_arm32 298ifeq ($(CFG_ARM64_core),y) 299supported-ta-targets += ta_arm64 300endif 301endif 302 303ta-targets := $(if $(CFG_USER_TA_TARGETS),$(filter $(supported-ta-targets),$(CFG_USER_TA_TARGETS)),$(supported-ta-targets)) 304unsup-targets := $(filter-out $(ta-targets),$(CFG_USER_TA_TARGETS)) 305ifneq (,$(unsup-targets)) 306$(error CFG_USER_TA_TARGETS contains unsupported value(s): $(unsup-targets). Valid values: $(supported-ta-targets)) 307endif 308 309ifneq ($(filter ta_arm32,$(ta-targets)),) 310# Variables for ta-target/sm "ta_arm32" 311CFG_ARM32_ta_arm32 := y 312arch-bits-ta_arm32 := 32 313ta_arm32-platform-cppflags += $(arm32-platform-cppflags) 314ta_arm32-platform-cflags += $(arm32-platform-cflags) 315ta_arm32-platform-cflags += $(platform-cflags-optimization) 316ta_arm32-platform-cflags += $(platform-cflags-debug-info) 317ta_arm32-platform-cflags += -fpic 318 319# Thumb mode doesn't support function graph tracing due to missing 320# frame pointer support required to trace function call chain. So 321# rather compile in ARM mode if function tracing is enabled. 322ifeq ($(CFG_FTRACE_SUPPORT),y) 323ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-arm) 324else 325ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-thumb) 326endif 327 328ifeq ($(arm32-platform-hard-float-enabled),y) 329ta_arm32-platform-cflags += $(arm32-platform-cflags-hard-float) 330else 331ta_arm32-platform-cflags += $(arm32-platform-cflags-no-hard-float) 332endif 333ifeq ($(CFG_UNWIND),y) 334ta_arm32-platform-cflags += -funwind-tables 335endif 336ta_arm32-platform-aflags += $(platform-aflags-generic) 337ta_arm32-platform-aflags += $(platform-aflags-debug-info) 338ta_arm32-platform-aflags += $(arm32-platform-aflags) 339 340ta_arm32-platform-cxxflags += -fpic 341ta_arm32-platform-cxxflags += $(arm32-platform-cxxflags) 342ta_arm32-platform-cxxflags += $(platform-cflags-optimization) 343ta_arm32-platform-cxxflags += $(platform-cflags-debug-info) 344 345ifeq ($(arm32-platform-hard-float-enabled),y) 346ta_arm32-platform-cxxflags += $(arm32-platform-cflags-hard-float) 347else 348ta_arm32-platform-cxxflags += $(arm32-platform-cflags-no-hard-float) 349endif 350 351ta-mk-file-export-vars-ta_arm32 += CFG_ARM32_ta_arm32 352ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cppflags 353ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cflags 354ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-aflags 355ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cxxflags 356 357ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE ?= arm-linux-gnueabihf-_nl_ 358ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE32 ?= $$(CROSS_COMPILE)_nl_ 359ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE_ta_arm32 ?= $$(CROSS_COMPILE32)_nl_ 360ta-mk-file-export-add-ta_arm32 += COMPILER ?= gcc_nl_ 361ta-mk-file-export-add-ta_arm32 += COMPILER_ta_arm32 ?= $$(COMPILER)_nl_ 362ta-mk-file-export-add-ta_arm32 += PYTHON3 ?= python3_nl_ 363endif 364 365ifneq ($(filter ta_arm64,$(ta-targets)),) 366# Variables for ta-target/sm "ta_arm64" 367CFG_ARM64_ta_arm64 := y 368arch-bits-ta_arm64 := 64 369ta_arm64-platform-cppflags += $(arm64-platform-cppflags) 370ta_arm64-platform-cflags += $(arm64-platform-cflags) 371ta_arm64-platform-cflags += $(platform-cflags-optimization) 372ta_arm64-platform-cflags += $(platform-cflags-debug-info) 373ta_arm64-platform-cflags += -fpic 374ta_arm64-platform-cflags += $(arm64-platform-cflags-generic) 375ifeq ($(arm64-platform-hard-float-enabled),y) 376ta_arm64-platform-cflags += $(arm64-platform-cflags-hard-float) 377else 378ta_arm64-platform-cflags += $(arm64-platform-cflags-no-hard-float) 379endif 380ta_arm64-platform-aflags += $(platform-aflags-generic) 381ta_arm64-platform-aflags += $(platform-aflags-debug-info) 382ta_arm64-platform-aflags += $(arm64-platform-aflags) 383 384ta_arm64-platform-cxxflags += -fpic 385ta_arm64-platform-cxxflags += $(platform-cflags-optimization) 386ta_arm64-platform-cxxflags += $(platform-cflags-debug-info) 387 388ifeq ($(CFG_TA_PAUTH),y) 389bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf) 390endif 391 392ifeq ($(CFG_TA_BTI),y) 393bp-ta-opt := $(call cc-option,-mbranch-protection=bti) 394endif 395 396ifeq (y-y,$(CFG_TA_PAUTH)-$(CFG_TA_BTI)) 397bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf+bti) 398endif 399 400ifeq (y,$(filter $(CFG_TA_BTI) $(CFG_TA_PAUTH),y)) 401ifeq (,$(bp-ta-opt)) 402$(error -mbranch-protection not supported) 403endif 404ta_arm64-platform-cflags += $(bp-ta-opt) 405endif 406 407ta-mk-file-export-vars-ta_arm64 += CFG_ARM64_ta_arm64 408ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cppflags 409ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cflags 410ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-aflags 411ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cxxflags 412 413ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE64 ?= $$(CROSS_COMPILE)_nl_ 414ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE_ta_arm64 ?= $$(CROSS_COMPILE64)_nl_ 415ta-mk-file-export-add-ta_arm64 += COMPILER ?= gcc_nl_ 416ta-mk-file-export-add-ta_arm64 += COMPILER_ta_arm64 ?= $$(COMPILER)_nl_ 417ta-mk-file-export-add-ta_arm64 += PYTHON3 ?= python3_nl_ 418endif 419 420# Set cross compiler prefix for each TA target 421$(foreach sm, $(ta-targets), $(eval CROSS_COMPILE_$(sm) ?= $(CROSS_COMPILE$(arch-bits-$(sm))))) 422 423arm32-sysreg-txt = core/arch/arm/kernel/arm32_sysreg.txt 424arm32-sysregs-$(arm32-sysreg-txt)-h := arm32_sysreg.h 425arm32-sysregs-$(arm32-sysreg-txt)-s := arm32_sysreg.S 426arm32-sysregs += $(arm32-sysreg-txt) 427 428ifeq ($(CFG_ARM_GICV3),y) 429arm32-gicv3-sysreg-txt = core/arch/arm/kernel/arm32_gicv3_sysreg.txt 430arm32-sysregs-$(arm32-gicv3-sysreg-txt)-h := arm32_gicv3_sysreg.h 431arm32-sysregs-$(arm32-gicv3-sysreg-txt)-s := arm32_gicv3_sysreg.S 432arm32-sysregs += $(arm32-gicv3-sysreg-txt) 433endif 434 435arm32-sysregs-out := $(out-dir)/$(sm)/include/generated 436 437define process-arm32-sysreg 438FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 439cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 440 441$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h): $(1) scripts/arm32_sysreg.py 442 @$(cmd-echo-silent) ' GEN $$@' 443 $(q)mkdir -p $$(dir $$@) 444 $(q)scripts/arm32_sysreg.py --guard __$$(arm32-sysregs-$(1)-h) \ 445 < $$< > $$@ 446 447FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 448cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 449 450$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s): $(1) scripts/arm32_sysreg.py 451 @$(cmd-echo-silent) ' GEN $$@' 452 $(q)mkdir -p $$(dir $$@) 453 $(q)scripts/arm32_sysreg.py --s_file < $$< > $$@ 454endef #process-arm32-sysreg 455 456$(foreach sr, $(arm32-sysregs), $(eval $(call process-arm32-sysreg,$(sr)))) 457