1# Setup compiler for the core module 2ifeq ($(CFG_ARM64_core),y) 3arch-bits-core := 64 4else 5arch-bits-core := 32 6endif 7CROSS_COMPILE_core := $(CROSS_COMPILE$(arch-bits-core)) 8COMPILER_core := $(COMPILER) 9include mk/$(COMPILER_core).mk 10 11# Defines the cc-option macro using the compiler set for the core module 12include mk/cc-option.mk 13 14# Size of emulated TrustZone protected SRAM, 448 kB. 15# Only applicable when paging is enabled. 16CFG_CORE_TZSRAM_EMUL_SIZE ?= 458752 17 18ifneq ($(CFG_LPAE_ADDR_SPACE_SIZE),) 19$(warning Error: CFG_LPAE_ADDR_SPACE_SIZE is not supported any longer) 20$(error Error: Please use CFG_LPAE_ADDR_SPACE_BITS instead) 21endif 22 23CFG_LPAE_ADDR_SPACE_BITS ?= 32 24 25CFG_MMAP_REGIONS ?= 13 26CFG_RESERVED_VASPACE_SIZE ?= (1024 * 1024 * 10) 27 28ifeq ($(CFG_ARM64_core),y) 29CFG_KERN_LINKER_FORMAT ?= elf64-littleaarch64 30CFG_KERN_LINKER_ARCH ?= aarch64 31# TCR_EL1.IPS needs to be initialized according to the largest physical 32# address that we need to map. 33# Physical address size 34# 32 bits, 4GB. 35# 36 bits, 64GB. 36# (etc.) 37CFG_CORE_ARM64_PA_BITS ?= 32 38else 39ifeq ($(CFG_ARM32_core),y) 40CFG_KERN_LINKER_FORMAT ?= elf32-littlearm 41CFG_KERN_LINKER_ARCH ?= arm 42else 43$(error Error: CFG_ARM64_core or CFG_ARM32_core should be defined) 44endif 45endif 46 47ifeq ($(CFG_TA_FLOAT_SUPPORT),y) 48# Use hard-float for floating point support in user TAs instead of 49# soft-float 50CFG_WITH_VFP ?= y 51ifeq ($(CFG_ARM64_core),y) 52# AArch64 has no fallback to soft-float 53$(call force,CFG_WITH_VFP,y) 54endif 55ifeq ($(CFG_WITH_VFP),y) 56arm64-platform-hard-float-enabled := y 57ifneq ($(CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT),y) 58arm32-platform-hard-float-enabled := y 59endif 60endif 61endif 62 63# Adds protection against CVE-2017-5715 also know as Spectre 64# (https://spectreattack.com) 65# See also https://developer.arm.com/-/media/Files/pdf/Cache_Speculation_Side-channels.pdf 66# Variant 2 67CFG_CORE_WORKAROUND_SPECTRE_BP ?= y 68# Same as CFG_CORE_WORKAROUND_SPECTRE_BP but targeting exceptions from 69# secure EL0 instead of non-secure world. 70CFG_CORE_WORKAROUND_SPECTRE_BP_SEC ?= $(CFG_CORE_WORKAROUND_SPECTRE_BP) 71 72# Adds protection against a tool like Cachegrab 73# (https://github.com/nccgroup/cachegrab), which uses non-secure interrupts 74# to prime and later analyze the L1D, L1I and BTB caches to gain 75# information from secure world execution. 76CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME ?= y 77ifeq ($(CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME),y) 78$(call force,CFG_CORE_WORKAROUND_SPECTRE_BP,y,Required by CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME) 79endif 80 81CFG_CORE_RWDATA_NOEXEC ?= y 82CFG_CORE_RODATA_NOEXEC ?= n 83ifeq ($(CFG_CORE_RODATA_NOEXEC),y) 84$(call force,CFG_CORE_RWDATA_NOEXEC,y) 85endif 86# 'y' to set the Alignment Check Enable bit in SCTLR/SCTLR_EL1, 'n' to clear it 87CFG_SCTLR_ALIGNMENT_CHECK ?= n 88 89ifeq ($(CFG_CORE_LARGE_PHYS_ADDR),y) 90$(call force,CFG_WITH_LPAE,y) 91endif 92 93# SPMC configuration "S-EL1 SPMC" where SPM Core is implemented at S-EL1, 94# that is, OP-TEE. 95# Note that this is an experimental feature, ABIs etc may have incompatible 96# changes 97ifeq ($(CFG_CORE_SEL1_SPMC),y) 98$(call force,CFG_CORE_FFA,y) 99$(call force,CFG_CORE_SEL2_SPMC,n) 100endif 101# SPMC configuration "S-EL2 SPMC" where SPM Core is implemented at S-EL2, 102# that is, the hypervisor sandboxing OP-TEE 103ifeq ($(CFG_CORE_SEL2_SPMC),y) 104$(call force,CFG_CORE_FFA,y) 105endif 106 107# Unmaps all kernel mode code except the code needed to take exceptions 108# from user space and restore kernel mode mapping again. This gives more 109# strict control over what is accessible while in user mode. 110# Addresses CVE-2017-5715 (aka Meltdown) known to affect Arm Cortex-A75 111CFG_CORE_UNMAP_CORE_AT_EL0 ?= y 112 113# Initialize PMCR.DP to 1 to prohibit cycle counting in secure state, and 114# save/restore PMCR during world switch. 115CFG_SM_NO_CYCLE_COUNTING ?= y 116 117ifeq ($(CFG_ARM32_core),y) 118# Configration directive related to ARMv7 optee boot arguments. 119# CFG_PAGEABLE_ADDR: if defined, forces pageable data physical address. 120# CFG_NS_ENTRY_ADDR: if defined, forces NS World physical entry address. 121# CFG_DT_ADDR: if defined, forces Device Tree data physical address. 122endif 123 124core-platform-cppflags += -I$(arch-dir)/include 125core-platform-subdirs += \ 126 $(addprefix $(arch-dir)/, kernel crypto mm tee) $(platform-dir) 127 128ifneq ($(CFG_WITH_ARM_TRUSTED_FW),y) 129core-platform-subdirs += $(arch-dir)/sm 130endif 131 132arm64-platform-cppflags += -DARM64=1 -D__LP64__=1 133arm32-platform-cppflags += -DARM32=1 -D__ILP32__=1 134 135platform-cflags-generic ?= -ffunction-sections -fdata-sections -pipe 136platform-aflags-generic ?= -pipe 137 138arm32-platform-aflags += -marm 139 140arm32-platform-cflags-no-hard-float ?= -mfloat-abi=soft 141arm32-platform-cflags-hard-float ?= -mfloat-abi=hard -funsafe-math-optimizations 142arm32-platform-cflags-generic-thumb ?= -mthumb \ 143 -fno-short-enums -fno-common -mno-unaligned-access 144arm32-platform-cflags-generic-arm ?= -marm -fno-omit-frame-pointer -mapcs \ 145 -fno-short-enums -fno-common -mno-unaligned-access 146arm32-platform-aflags-no-hard-float ?= 147 148arm64-platform-cflags-no-hard-float ?= -mgeneral-regs-only 149arm64-platform-cflags-hard-float ?= 150arm64-platform-cflags-generic := -mstrict-align $(call cc-option,-mno-outline-atomics,) 151 152ifeq ($(DEBUG),1) 153# For backwards compatibility 154$(call force,CFG_CC_OPT_LEVEL,0) 155$(call force,CFG_DEBUG_INFO,y) 156endif 157ifeq ($(CFG_CC_OPTIMIZE_FOR_SIZE),n) 158# For backwards compatibility 159$(call force,CFG_CC_OPT_LEVEL,0) 160endif 161 162# Optimize for size by default, usually gives good performance too 163CFG_CC_OPT_LEVEL ?= s 164platform-cflags-optimization ?= -O$(CFG_CC_OPT_LEVEL) 165 166CFG_DEBUG_INFO ?= y 167ifeq ($(CFG_DEBUG_INFO),y) 168platform-cflags-debug-info ?= -g3 169platform-aflags-debug-info ?= -g 170endif 171 172core-platform-cflags += $(platform-cflags-optimization) 173core-platform-cflags += $(platform-cflags-generic) 174core-platform-cflags += $(platform-cflags-debug-info) 175 176core-platform-aflags += $(platform-aflags-generic) 177core-platform-aflags += $(platform-aflags-debug-info) 178 179ifeq ($(CFG_CORE_ASLR),y) 180core-platform-cflags += -fpie 181endif 182 183ifeq ($(CFG_ARM64_core),y) 184core-platform-cppflags += $(arm64-platform-cppflags) 185core-platform-cflags += $(arm64-platform-cflags) 186core-platform-cflags += $(arm64-platform-cflags-generic) 187core-platform-cflags += $(arm64-platform-cflags-no-hard-float) 188core-platform-aflags += $(arm64-platform-aflags) 189else 190core-platform-cppflags += $(arm32-platform-cppflags) 191core-platform-cflags += $(arm32-platform-cflags) 192core-platform-cflags += $(arm32-platform-cflags-no-hard-float) 193ifeq ($(CFG_UNWIND),y) 194core-platform-cflags += -funwind-tables 195endif 196ifeq ($(CFG_SYSCALL_FTRACE),y) 197core-platform-cflags += $(arm32-platform-cflags-generic-arm) 198else 199core-platform-cflags += $(arm32-platform-cflags-generic-thumb) 200endif 201core-platform-aflags += $(core_arm32-platform-aflags) 202core-platform-aflags += $(arm32-platform-aflags) 203endif 204 205# Provide default supported-ta-targets if not set by the platform config 206ifeq (,$(supported-ta-targets)) 207supported-ta-targets = ta_arm32 208ifeq ($(CFG_ARM64_core),y) 209supported-ta-targets += ta_arm64 210endif 211endif 212 213ta-targets := $(if $(CFG_USER_TA_TARGETS),$(filter $(supported-ta-targets),$(CFG_USER_TA_TARGETS)),$(supported-ta-targets)) 214unsup-targets := $(filter-out $(ta-targets),$(CFG_USER_TA_TARGETS)) 215ifneq (,$(unsup-targets)) 216$(error CFG_USER_TA_TARGETS contains unsupported value(s): $(unsup-targets). Valid values: $(supported-ta-targets)) 217endif 218 219ifneq ($(filter ta_arm32,$(ta-targets)),) 220# Variables for ta-target/sm "ta_arm32" 221CFG_ARM32_ta_arm32 := y 222arch-bits-ta_arm32 := 32 223ta_arm32-platform-cppflags += $(arm32-platform-cppflags) 224ta_arm32-platform-cflags += $(arm32-platform-cflags) 225ta_arm32-platform-cflags += $(platform-cflags-optimization) 226ta_arm32-platform-cflags += $(platform-cflags-debug-info) 227ta_arm32-platform-cflags += -fpic 228 229# Thumb mode doesn't support function graph tracing due to missing 230# frame pointer support required to trace function call chain. So 231# rather compile in ARM mode if function tracing is enabled. 232ifeq ($(CFG_FTRACE_SUPPORT),y) 233ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-arm) 234else 235ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-thumb) 236endif 237 238ifeq ($(arm32-platform-hard-float-enabled),y) 239ta_arm32-platform-cflags += $(arm32-platform-cflags-hard-float) 240else 241ta_arm32-platform-cflags += $(arm32-platform-cflags-no-hard-float) 242endif 243ifeq ($(CFG_UNWIND),y) 244ta_arm32-platform-cflags += -funwind-tables 245endif 246ta_arm32-platform-aflags += $(platform-aflags-generic) 247ta_arm32-platform-aflags += $(platform-aflags-debug-info) 248ta_arm32-platform-aflags += $(arm32-platform-aflags) 249 250ta_arm32-platform-cxxflags += -fpic 251ta_arm32-platform-cxxflags += $(arm32-platform-cxxflags) 252ta_arm32-platform-cxxflags += $(platform-cflags-optimization) 253ta_arm32-platform-cxxflags += $(platform-cflags-debug-info) 254 255ifeq ($(arm32-platform-hard-float-enabled),y) 256ta_arm32-platform-cxxflags += $(arm32-platform-cflags-hard-float) 257else 258ta_arm32-platform-cxxflags += $(arm32-platform-cflags-no-hard-float) 259endif 260 261ta-mk-file-export-vars-ta_arm32 += CFG_ARM32_ta_arm32 262ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cppflags 263ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cflags 264ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-aflags 265ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cxxflags 266 267ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE ?= arm-linux-gnueabihf-_nl_ 268ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE32 ?= $$(CROSS_COMPILE)_nl_ 269ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE_ta_arm32 ?= $$(CROSS_COMPILE32)_nl_ 270ta-mk-file-export-add-ta_arm32 += COMPILER ?= gcc_nl_ 271ta-mk-file-export-add-ta_arm32 += COMPILER_ta_arm32 ?= $$(COMPILER)_nl_ 272ta-mk-file-export-add-ta_arm32 += PYTHON3 ?= python3_nl_ 273endif 274 275ifneq ($(filter ta_arm64,$(ta-targets)),) 276# Variables for ta-target/sm "ta_arm64" 277CFG_ARM64_ta_arm64 := y 278arch-bits-ta_arm64 := 64 279ta_arm64-platform-cppflags += $(arm64-platform-cppflags) 280ta_arm64-platform-cflags += $(arm64-platform-cflags) 281ta_arm64-platform-cflags += $(platform-cflags-optimization) 282ta_arm64-platform-cflags += $(platform-cflags-debug-info) 283ta_arm64-platform-cflags += -fpic 284ta_arm64-platform-cflags += $(arm64-platform-cflags-generic) 285ifeq ($(arm64-platform-hard-float-enabled),y) 286ta_arm64-platform-cflags += $(arm64-platform-cflags-hard-float) 287else 288ta_arm64-platform-cflags += $(arm64-platform-cflags-no-hard-float) 289endif 290ta_arm64-platform-aflags += $(platform-aflags-generic) 291ta_arm64-platform-aflags += $(platform-aflags-debug-info) 292ta_arm64-platform-aflags += $(arm64-platform-aflags) 293 294ta_arm64-platform-cxxflags += -fpic 295ta_arm64-platform-cxxflags += $(platform-cflags-optimization) 296ta_arm64-platform-cxxflags += $(platform-cflags-debug-info) 297 298ta-mk-file-export-vars-ta_arm64 += CFG_ARM64_ta_arm64 299ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cppflags 300ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cflags 301ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-aflags 302ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cxxflags 303 304ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE64 ?= $$(CROSS_COMPILE)_nl_ 305ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE_ta_arm64 ?= $$(CROSS_COMPILE64)_nl_ 306ta-mk-file-export-add-ta_arm64 += COMPILER ?= gcc_nl_ 307ta-mk-file-export-add-ta_arm64 += COMPILER_ta_arm64 ?= $$(COMPILER)_nl_ 308ta-mk-file-export-add-ta_arm64 += PYTHON3 ?= python3_nl_ 309endif 310 311# Set cross compiler prefix for each TA target 312$(foreach sm, $(ta-targets), $(eval CROSS_COMPILE_$(sm) ?= $(CROSS_COMPILE$(arch-bits-$(sm))))) 313 314arm32-sysreg-txt = core/arch/arm/kernel/arm32_sysreg.txt 315arm32-sysregs-$(arm32-sysreg-txt)-h := arm32_sysreg.h 316arm32-sysregs-$(arm32-sysreg-txt)-s := arm32_sysreg.S 317arm32-sysregs += $(arm32-sysreg-txt) 318 319ifeq ($(CFG_ARM_GICV3),y) 320arm32-gicv3-sysreg-txt = core/arch/arm/kernel/arm32_gicv3_sysreg.txt 321arm32-sysregs-$(arm32-gicv3-sysreg-txt)-h := arm32_gicv3_sysreg.h 322arm32-sysregs-$(arm32-gicv3-sysreg-txt)-s := arm32_gicv3_sysreg.S 323arm32-sysregs += $(arm32-gicv3-sysreg-txt) 324endif 325 326arm32-sysregs-out := $(out-dir)/$(sm)/include/generated 327 328define process-arm32-sysreg 329FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 330cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 331 332$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h): $(1) scripts/arm32_sysreg.py 333 @$(cmd-echo-silent) ' GEN $$@' 334 $(q)mkdir -p $$(dir $$@) 335 $(q)scripts/arm32_sysreg.py --guard __$$(arm32-sysregs-$(1)-h) \ 336 < $$< > $$@ 337 338FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 339cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 340 341$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s): $(1) scripts/arm32_sysreg.py 342 @$(cmd-echo-silent) ' GEN $$@' 343 $(q)mkdir -p $$(dir $$@) 344 $(q)scripts/arm32_sysreg.py --s_file < $$< > $$@ 345endef #process-arm32-sysreg 346 347$(foreach sr, $(arm32-sysregs), $(eval $(call process-arm32-sysreg,$(sr)))) 348