1# Setup compiler for the core module 2ifeq ($(CFG_ARM64_core),y) 3arch-bits-core := 64 4else 5arch-bits-core := 32 6endif 7CROSS_COMPILE_core := $(CROSS_COMPILE$(arch-bits-core)) 8COMPILER_core := $(COMPILER) 9include mk/$(COMPILER_core).mk 10 11# Defines the cc-option macro using the compiler set for the core module 12include mk/cc-option.mk 13 14# Size of emulated TrustZone protected SRAM, 448 kB. 15# Only applicable when paging is enabled. 16CFG_CORE_TZSRAM_EMUL_SIZE ?= 458752 17 18ifneq ($(CFG_LPAE_ADDR_SPACE_SIZE),) 19$(warning Error: CFG_LPAE_ADDR_SPACE_SIZE is not supported any longer) 20$(error Error: Please use CFG_LPAE_ADDR_SPACE_BITS instead) 21endif 22 23CFG_LPAE_ADDR_SPACE_BITS ?= 32 24 25CFG_MMAP_REGIONS ?= 13 26CFG_RESERVED_VASPACE_SIZE ?= (1024 * 1024 * 10) 27 28ifeq ($(CFG_ARM64_core),y) 29CFG_KERN_LINKER_FORMAT ?= elf64-littleaarch64 30CFG_KERN_LINKER_ARCH ?= aarch64 31# TCR_EL1.IPS needs to be initialized according to the largest physical 32# address that we need to map. 33# Physical address size 34# 32 bits, 4GB. 35# 36 bits, 64GB. 36# (etc.) 37CFG_CORE_ARM64_PA_BITS ?= 32 38else 39ifeq ($(CFG_ARM32_core),y) 40CFG_KERN_LINKER_FORMAT ?= elf32-littlearm 41CFG_KERN_LINKER_ARCH ?= arm 42else 43$(error Error: CFG_ARM64_core or CFG_ARM32_core should be defined) 44endif 45endif 46 47ifeq ($(CFG_TA_FLOAT_SUPPORT),y) 48# Use hard-float for floating point support in user TAs instead of 49# soft-float 50CFG_WITH_VFP ?= y 51ifeq ($(CFG_ARM64_core),y) 52# AArch64 has no fallback to soft-float 53$(call force,CFG_WITH_VFP,y) 54endif 55ifeq ($(CFG_WITH_VFP),y) 56arm64-platform-hard-float-enabled := y 57ifneq ($(CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT),y) 58arm32-platform-hard-float-enabled := y 59endif 60endif 61endif 62 63# Adds protection against CVE-2017-5715 also know as Spectre 64# (https://spectreattack.com) 65# See also https://developer.arm.com/-/media/Files/pdf/Cache_Speculation_Side-channels.pdf 66# Variant 2 67CFG_CORE_WORKAROUND_SPECTRE_BP ?= y 68# Same as CFG_CORE_WORKAROUND_SPECTRE_BP but targeting exceptions from 69# secure EL0 instead of non-secure world. 70CFG_CORE_WORKAROUND_SPECTRE_BP_SEC ?= $(CFG_CORE_WORKAROUND_SPECTRE_BP) 71 72# Adds protection against a tool like Cachegrab 73# (https://github.com/nccgroup/cachegrab), which uses non-secure interrupts 74# to prime and later analyze the L1D, L1I and BTB caches to gain 75# information from secure world execution. 76CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME ?= y 77ifeq ($(CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME),y) 78$(call force,CFG_CORE_WORKAROUND_SPECTRE_BP,y,Required by CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME) 79endif 80 81CFG_CORE_RWDATA_NOEXEC ?= y 82CFG_CORE_RODATA_NOEXEC ?= n 83ifeq ($(CFG_CORE_RODATA_NOEXEC),y) 84$(call force,CFG_CORE_RWDATA_NOEXEC,y) 85endif 86# 'y' to set the Alignment Check Enable bit in SCTLR/SCTLR_EL1, 'n' to clear it 87CFG_SCTLR_ALIGNMENT_CHECK ?= n 88 89ifeq ($(CFG_CORE_LARGE_PHYS_ADDR),y) 90$(call force,CFG_WITH_LPAE,y) 91endif 92 93# SPMC configuration "S-EL1 SPMC" where SPM Core is implemented at S-EL1, 94# that is, OP-TEE. 95# Note that this is an experimental feature, ABIs etc may have incompatible 96# changes 97ifeq ($(CFG_CORE_SEL1_SPMC),y) 98$(call force,CFG_CORE_FFA,y) 99$(call force,CFG_CORE_SEL2_SPMC,n) 100endif 101# SPMC configuration "S-EL2 SPMC" where SPM Core is implemented at S-EL2, 102# that is, the hypervisor sandboxing OP-TEE 103ifeq ($(CFG_CORE_SEL2_SPMC),y) 104$(call force,CFG_CORE_FFA,y) 105endif 106 107# Unmaps all kernel mode code except the code needed to take exceptions 108# from user space and restore kernel mode mapping again. This gives more 109# strict control over what is accessible while in user mode. 110# Addresses CVE-2017-5715 (aka Meltdown) known to affect Arm Cortex-A75 111CFG_CORE_UNMAP_CORE_AT_EL0 ?= y 112 113# Initialize PMCR.DP to 1 to prohibit cycle counting in secure state, and 114# save/restore PMCR during world switch. 115CFG_SM_NO_CYCLE_COUNTING ?= y 116 117 118# CFG_CORE_ASYNC_NOTIF_GIC_INTID is defined by the platform to some free 119# interrupt. Setting it to a non-zero number enables support for using an 120# Arm-GIC to notify normal world. This config variable should use a value 121# larger the 32 to make it of the type SPI. 122# Note that asynchronous notifactions must be enabled with 123# CFG_CORE_ASYNC_NOTIF=y for this variable to be used. 124CFG_CORE_ASYNC_NOTIF_GIC_INTID ?= 0 125 126ifeq ($(CFG_ARM32_core),y) 127# Configration directive related to ARMv7 optee boot arguments. 128# CFG_PAGEABLE_ADDR: if defined, forces pageable data physical address. 129# CFG_NS_ENTRY_ADDR: if defined, forces NS World physical entry address. 130# CFG_DT_ADDR: if defined, forces Device Tree data physical address. 131endif 132 133core-platform-cppflags += -I$(arch-dir)/include 134core-platform-subdirs += \ 135 $(addprefix $(arch-dir)/, kernel crypto mm tee) $(platform-dir) 136 137ifneq ($(CFG_WITH_ARM_TRUSTED_FW),y) 138core-platform-subdirs += $(arch-dir)/sm 139endif 140 141arm64-platform-cppflags += -DARM64=1 -D__LP64__=1 142arm32-platform-cppflags += -DARM32=1 -D__ILP32__=1 143 144platform-cflags-generic ?= -ffunction-sections -fdata-sections -pipe 145platform-aflags-generic ?= -pipe 146 147arm32-platform-aflags += -marm 148 149arm32-platform-cflags-no-hard-float ?= -mfloat-abi=soft 150arm32-platform-cflags-hard-float ?= -mfloat-abi=hard -funsafe-math-optimizations 151arm32-platform-cflags-generic-thumb ?= -mthumb \ 152 -fno-short-enums -fno-common -mno-unaligned-access 153arm32-platform-cflags-generic-arm ?= -marm -fno-omit-frame-pointer -mapcs \ 154 -fno-short-enums -fno-common -mno-unaligned-access 155arm32-platform-aflags-no-hard-float ?= 156 157arm64-platform-cflags-no-hard-float ?= -mgeneral-regs-only 158arm64-platform-cflags-hard-float ?= 159arm64-platform-cflags-generic := -mstrict-align $(call cc-option,-mno-outline-atomics,) 160 161platform-cflags-optimization ?= -O$(CFG_CC_OPT_LEVEL) 162 163ifeq ($(CFG_DEBUG_INFO),y) 164platform-cflags-debug-info ?= -g3 165platform-aflags-debug-info ?= -g 166endif 167 168core-platform-cflags += $(platform-cflags-optimization) 169core-platform-cflags += $(platform-cflags-generic) 170core-platform-cflags += $(platform-cflags-debug-info) 171 172core-platform-aflags += $(platform-aflags-generic) 173core-platform-aflags += $(platform-aflags-debug-info) 174 175ifeq ($(CFG_CORE_ASLR),y) 176core-platform-cflags += -fpie 177endif 178 179ifeq ($(CFG_CORE_BTI),y) 180bti-opt := $(call cc-option,-mbranch-protection=bti) 181ifeq (,$(bti-opt)) 182$(error -mbranch-protection=bti not supported) 183endif 184core-platform-cflags += $(bti-opt) 185endif 186 187ifeq ($(CFG_ARM64_core),y) 188core-platform-cppflags += $(arm64-platform-cppflags) 189core-platform-cflags += $(arm64-platform-cflags) 190core-platform-cflags += $(arm64-platform-cflags-generic) 191core-platform-cflags += $(arm64-platform-cflags-no-hard-float) 192core-platform-aflags += $(arm64-platform-aflags) 193else 194core-platform-cppflags += $(arm32-platform-cppflags) 195core-platform-cflags += $(arm32-platform-cflags) 196core-platform-cflags += $(arm32-platform-cflags-no-hard-float) 197ifeq ($(CFG_UNWIND),y) 198core-platform-cflags += -funwind-tables 199endif 200ifeq ($(CFG_SYSCALL_FTRACE),y) 201core-platform-cflags += $(arm32-platform-cflags-generic-arm) 202else 203core-platform-cflags += $(arm32-platform-cflags-generic-thumb) 204endif 205core-platform-aflags += $(core_arm32-platform-aflags) 206core-platform-aflags += $(arm32-platform-aflags) 207endif 208 209# Provide default supported-ta-targets if not set by the platform config 210ifeq (,$(supported-ta-targets)) 211supported-ta-targets = ta_arm32 212ifeq ($(CFG_ARM64_core),y) 213supported-ta-targets += ta_arm64 214endif 215endif 216 217ta-targets := $(if $(CFG_USER_TA_TARGETS),$(filter $(supported-ta-targets),$(CFG_USER_TA_TARGETS)),$(supported-ta-targets)) 218unsup-targets := $(filter-out $(ta-targets),$(CFG_USER_TA_TARGETS)) 219ifneq (,$(unsup-targets)) 220$(error CFG_USER_TA_TARGETS contains unsupported value(s): $(unsup-targets). Valid values: $(supported-ta-targets)) 221endif 222 223ifneq ($(filter ta_arm32,$(ta-targets)),) 224# Variables for ta-target/sm "ta_arm32" 225CFG_ARM32_ta_arm32 := y 226arch-bits-ta_arm32 := 32 227ta_arm32-platform-cppflags += $(arm32-platform-cppflags) 228ta_arm32-platform-cflags += $(arm32-platform-cflags) 229ta_arm32-platform-cflags += $(platform-cflags-optimization) 230ta_arm32-platform-cflags += $(platform-cflags-debug-info) 231ta_arm32-platform-cflags += -fpic 232 233# Thumb mode doesn't support function graph tracing due to missing 234# frame pointer support required to trace function call chain. So 235# rather compile in ARM mode if function tracing is enabled. 236ifeq ($(CFG_FTRACE_SUPPORT),y) 237ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-arm) 238else 239ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-thumb) 240endif 241 242ifeq ($(arm32-platform-hard-float-enabled),y) 243ta_arm32-platform-cflags += $(arm32-platform-cflags-hard-float) 244else 245ta_arm32-platform-cflags += $(arm32-platform-cflags-no-hard-float) 246endif 247ifeq ($(CFG_UNWIND),y) 248ta_arm32-platform-cflags += -funwind-tables 249endif 250ta_arm32-platform-aflags += $(platform-aflags-generic) 251ta_arm32-platform-aflags += $(platform-aflags-debug-info) 252ta_arm32-platform-aflags += $(arm32-platform-aflags) 253 254ta_arm32-platform-cxxflags += -fpic 255ta_arm32-platform-cxxflags += $(arm32-platform-cxxflags) 256ta_arm32-platform-cxxflags += $(platform-cflags-optimization) 257ta_arm32-platform-cxxflags += $(platform-cflags-debug-info) 258 259ifeq ($(arm32-platform-hard-float-enabled),y) 260ta_arm32-platform-cxxflags += $(arm32-platform-cflags-hard-float) 261else 262ta_arm32-platform-cxxflags += $(arm32-platform-cflags-no-hard-float) 263endif 264 265ta-mk-file-export-vars-ta_arm32 += CFG_ARM32_ta_arm32 266ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cppflags 267ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cflags 268ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-aflags 269ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cxxflags 270 271ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE ?= arm-linux-gnueabihf-_nl_ 272ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE32 ?= $$(CROSS_COMPILE)_nl_ 273ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE_ta_arm32 ?= $$(CROSS_COMPILE32)_nl_ 274ta-mk-file-export-add-ta_arm32 += COMPILER ?= gcc_nl_ 275ta-mk-file-export-add-ta_arm32 += COMPILER_ta_arm32 ?= $$(COMPILER)_nl_ 276ta-mk-file-export-add-ta_arm32 += PYTHON3 ?= python3_nl_ 277endif 278 279ifneq ($(filter ta_arm64,$(ta-targets)),) 280# Variables for ta-target/sm "ta_arm64" 281CFG_ARM64_ta_arm64 := y 282arch-bits-ta_arm64 := 64 283ta_arm64-platform-cppflags += $(arm64-platform-cppflags) 284ta_arm64-platform-cflags += $(arm64-platform-cflags) 285ta_arm64-platform-cflags += $(platform-cflags-optimization) 286ta_arm64-platform-cflags += $(platform-cflags-debug-info) 287ta_arm64-platform-cflags += -fpic 288ta_arm64-platform-cflags += $(arm64-platform-cflags-generic) 289ifeq ($(arm64-platform-hard-float-enabled),y) 290ta_arm64-platform-cflags += $(arm64-platform-cflags-hard-float) 291else 292ta_arm64-platform-cflags += $(arm64-platform-cflags-no-hard-float) 293endif 294ta_arm64-platform-aflags += $(platform-aflags-generic) 295ta_arm64-platform-aflags += $(platform-aflags-debug-info) 296ta_arm64-platform-aflags += $(arm64-platform-aflags) 297 298ta_arm64-platform-cxxflags += -fpic 299ta_arm64-platform-cxxflags += $(platform-cflags-optimization) 300ta_arm64-platform-cxxflags += $(platform-cflags-debug-info) 301 302ifeq ($(CFG_TA_BTI),y) 303bti-ta-opt := $(call cc-option,-mbranch-protection=bti) 304ifeq (,$(bti-ta-opt)) 305$(error -mbranch-protection=bti not supported) 306endif 307ta_arm64-platform-cflags += $(bti-ta-opt) 308endif 309 310ta-mk-file-export-vars-ta_arm64 += CFG_ARM64_ta_arm64 311ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cppflags 312ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cflags 313ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-aflags 314ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cxxflags 315 316ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE64 ?= $$(CROSS_COMPILE)_nl_ 317ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE_ta_arm64 ?= $$(CROSS_COMPILE64)_nl_ 318ta-mk-file-export-add-ta_arm64 += COMPILER ?= gcc_nl_ 319ta-mk-file-export-add-ta_arm64 += COMPILER_ta_arm64 ?= $$(COMPILER)_nl_ 320ta-mk-file-export-add-ta_arm64 += PYTHON3 ?= python3_nl_ 321endif 322 323# Set cross compiler prefix for each TA target 324$(foreach sm, $(ta-targets), $(eval CROSS_COMPILE_$(sm) ?= $(CROSS_COMPILE$(arch-bits-$(sm))))) 325 326arm32-sysreg-txt = core/arch/arm/kernel/arm32_sysreg.txt 327arm32-sysregs-$(arm32-sysreg-txt)-h := arm32_sysreg.h 328arm32-sysregs-$(arm32-sysreg-txt)-s := arm32_sysreg.S 329arm32-sysregs += $(arm32-sysreg-txt) 330 331ifeq ($(CFG_ARM_GICV3),y) 332arm32-gicv3-sysreg-txt = core/arch/arm/kernel/arm32_gicv3_sysreg.txt 333arm32-sysregs-$(arm32-gicv3-sysreg-txt)-h := arm32_gicv3_sysreg.h 334arm32-sysregs-$(arm32-gicv3-sysreg-txt)-s := arm32_gicv3_sysreg.S 335arm32-sysregs += $(arm32-gicv3-sysreg-txt) 336endif 337 338arm32-sysregs-out := $(out-dir)/$(sm)/include/generated 339 340define process-arm32-sysreg 341FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 342cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 343 344$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h): $(1) scripts/arm32_sysreg.py 345 @$(cmd-echo-silent) ' GEN $$@' 346 $(q)mkdir -p $$(dir $$@) 347 $(q)scripts/arm32_sysreg.py --guard __$$(arm32-sysregs-$(1)-h) \ 348 < $$< > $$@ 349 350FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 351cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 352 353$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s): $(1) scripts/arm32_sysreg.py 354 @$(cmd-echo-silent) ' GEN $$@' 355 $(q)mkdir -p $$(dir $$@) 356 $(q)scripts/arm32_sysreg.py --s_file < $$< > $$@ 357endef #process-arm32-sysreg 358 359$(foreach sr, $(arm32-sysregs), $(eval $(call process-arm32-sysreg,$(sr)))) 360