1# Setup compiler for the core module 2ifeq ($(CFG_ARM64_core),y) 3arch-bits-core := 64 4else 5arch-bits-core := 32 6endif 7CROSS_COMPILE_core := $(CROSS_COMPILE$(arch-bits-core)) 8COMPILER_core := $(COMPILER) 9include mk/$(COMPILER_core).mk 10 11# Defines the cc-option macro using the compiler set for the core module 12include mk/cc-option.mk 13 14# Size of emulated TrustZone protected SRAM, 448 kB. 15# Only applicable when paging is enabled. 16CFG_CORE_TZSRAM_EMUL_SIZE ?= 458752 17 18ifneq ($(CFG_LPAE_ADDR_SPACE_SIZE),) 19$(warning Error: CFG_LPAE_ADDR_SPACE_SIZE is not supported any longer) 20$(error Error: Please use CFG_LPAE_ADDR_SPACE_BITS instead) 21endif 22 23CFG_LPAE_ADDR_SPACE_BITS ?= 32 24 25CFG_MMAP_REGIONS ?= 13 26CFG_RESERVED_VASPACE_SIZE ?= (1024 * 1024 * 10) 27 28ifeq ($(CFG_ARM64_core),y) 29ifeq ($(CFG_ARM32_core),y) 30$(error CFG_ARM64_core and CFG_ARM32_core cannot be both 'y') 31endif 32CFG_KERN_LINKER_FORMAT ?= elf64-littleaarch64 33CFG_KERN_LINKER_ARCH ?= aarch64 34# TCR_EL1.IPS needs to be initialized according to the largest physical 35# address that we need to map. 36# Physical address size 37# 32 bits, 4GB. 38# 36 bits, 64GB. 39# (etc.) 40CFG_CORE_ARM64_PA_BITS ?= 32 41$(call force,CFG_WITH_LPAE,y) 42else 43$(call force,CFG_ARM32_core,y) 44CFG_KERN_LINKER_FORMAT ?= elf32-littlearm 45CFG_KERN_LINKER_ARCH ?= arm 46endif 47 48ifeq ($(CFG_TA_FLOAT_SUPPORT),y) 49# Use hard-float for floating point support in user TAs instead of 50# soft-float 51CFG_WITH_VFP ?= y 52ifeq ($(CFG_ARM64_core),y) 53# AArch64 has no fallback to soft-float 54$(call force,CFG_WITH_VFP,y) 55endif 56ifeq ($(CFG_WITH_VFP),y) 57arm64-platform-hard-float-enabled := y 58ifneq ($(CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT),y) 59arm32-platform-hard-float-enabled := y 60endif 61endif 62endif 63 64# Adds protection against CVE-2017-5715 also know as Spectre 65# (https://spectreattack.com) 66# See also https://developer.arm.com/-/media/Files/pdf/Cache_Speculation_Side-channels.pdf 67# Variant 2 68CFG_CORE_WORKAROUND_SPECTRE_BP ?= y 69# Same as CFG_CORE_WORKAROUND_SPECTRE_BP but targeting exceptions from 70# secure EL0 instead of non-secure world, including mitigation for 71# CVE-2022-23960. 72CFG_CORE_WORKAROUND_SPECTRE_BP_SEC ?= $(CFG_CORE_WORKAROUND_SPECTRE_BP) 73 74# Adds protection against a tool like Cachegrab 75# (https://github.com/nccgroup/cachegrab), which uses non-secure interrupts 76# to prime and later analyze the L1D, L1I and BTB caches to gain 77# information from secure world execution. 78CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME ?= y 79ifeq ($(CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME),y) 80$(call force,CFG_CORE_WORKAROUND_SPECTRE_BP,y,Required by CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME) 81endif 82 83# Adds workarounds against if ARM core is configured with Non-maskable FIQ 84# (NMFI) support. This is indicated by SCTLR.NMFI being true. NMFI cannot be 85# disabled by software and as it affects atomic context end result will be 86# prohibiting FIQ signal usage in OP-TEE and applying some tweaks to make sure 87# FIQ is enabled in critical places. 88CFG_CORE_WORKAROUND_ARM_NMFI ?= n 89 90CFG_CORE_RWDATA_NOEXEC ?= y 91CFG_CORE_RODATA_NOEXEC ?= n 92ifeq ($(CFG_CORE_RODATA_NOEXEC),y) 93$(call force,CFG_CORE_RWDATA_NOEXEC,y) 94endif 95# 'y' to set the Alignment Check Enable bit in SCTLR/SCTLR_EL1, 'n' to clear it 96CFG_SCTLR_ALIGNMENT_CHECK ?= n 97 98ifeq ($(CFG_CORE_LARGE_PHYS_ADDR),y) 99$(call force,CFG_WITH_LPAE,y) 100endif 101 102# SPMC configuration "S-EL1 SPMC" where SPM Core is implemented at S-EL1, 103# that is, OP-TEE. 104ifeq ($(CFG_CORE_SEL1_SPMC),y) 105$(call force,CFG_CORE_FFA,y) 106$(call force,CFG_CORE_SEL2_SPMC,n) 107$(call force,CFG_CORE_EL3_SPMC,n) 108endif 109# SPMC configuration "S-EL2 SPMC" where SPM Core is implemented at S-EL2, 110# that is, the hypervisor sandboxing OP-TEE 111ifeq ($(CFG_CORE_SEL2_SPMC),y) 112$(call force,CFG_CORE_FFA,y) 113$(call force,CFG_CORE_SEL1_SPMC,n) 114$(call force,CFG_CORE_EL3_SPMC,n) 115CFG_CORE_HAFNIUM_INTC ?= y 116# Enable support in OP-TEE to relocate itself to allow it to run from a 117# physical address that differs from the link address 118CFG_CORE_PHYS_RELOCATABLE ?= y 119endif 120# SPMC configuration "EL3 SPMC" where SPM Core is implemented at EL3, that 121# is, in TF-A 122ifeq ($(CFG_CORE_EL3_SPMC),y) 123$(call force,CFG_CORE_FFA,y) 124$(call force,CFG_CORE_SEL2_SPMC,n) 125$(call force,CFG_CORE_SEL1_SPMC,n) 126endif 127 128ifeq ($(CFG_CORE_PHYS_RELOCATABLE)-$(CFG_WITH_PAGER),y-y) 129$(error CFG_CORE_PHYS_RELOCATABLE and CFG_WITH_PAGER are not compatible) 130endif 131ifeq ($(CFG_CORE_PHYS_RELOCATABLE),y) 132ifneq ($(CFG_CORE_SEL2_SPMC),y) 133$(error CFG_CORE_PHYS_RELOCATABLE depends on CFG_CORE_SEL2_SPMC) 134endif 135endif 136 137ifeq ($(CFG_CORE_FFA)-$(CFG_WITH_PAGER),y-y) 138$(error CFG_CORE_FFA and CFG_WITH_PAGER are not compatible) 139endif 140ifeq ($(CFG_GIC),y) 141ifeq ($(CFG_ARM_GICV3),y) 142$(call force,CFG_CORE_IRQ_IS_NATIVE_INTR,y) 143else 144$(call force,CFG_CORE_IRQ_IS_NATIVE_INTR,n) 145endif 146endif 147 148CFG_CORE_HAFNIUM_INTC ?= n 149ifeq ($(CFG_CORE_HAFNIUM_INTC),y) 150$(call force,CFG_CORE_IRQ_IS_NATIVE_INTR,y) 151endif 152 153# Selects if IRQ is used to signal native interrupt 154# if CFG_CORE_IRQ_IS_NATIVE_INTR == y: 155# IRQ signals a native interrupt pending 156# FIQ signals a foreign non-secure interrupt or a managed exit pending 157# else: (vice versa) 158# IRQ signals a foreign non-secure interrupt or a managed exit pending 159# FIQ signals a native interrupt pending 160CFG_CORE_IRQ_IS_NATIVE_INTR ?= n 161 162# Unmaps all kernel mode code except the code needed to take exceptions 163# from user space and restore kernel mode mapping again. This gives more 164# strict control over what is accessible while in user mode. 165# Addresses CVE-2017-5715 (aka Meltdown) known to affect Arm Cortex-A75 166CFG_CORE_UNMAP_CORE_AT_EL0 ?= y 167 168# Initialize PMCR.DP to 1 to prohibit cycle counting in secure state, and 169# save/restore PMCR during world switch. 170CFG_SM_NO_CYCLE_COUNTING ?= y 171 172 173# CFG_CORE_ASYNC_NOTIF_GIC_INTID is defined by the platform to some free 174# interrupt. Setting it to a non-zero number enables support for using an 175# Arm-GIC to notify normal world. This config variable should use a value 176# larger the 32 to make it of the type SPI. 177# Note that asynchronous notifactions must be enabled with 178# CFG_CORE_ASYNC_NOTIF=y for this variable to be used. 179CFG_CORE_ASYNC_NOTIF_GIC_INTID ?= 0 180 181ifeq ($(CFG_ARM32_core),y) 182# Configration directive related to ARMv7 optee boot arguments. 183# CFG_PAGEABLE_ADDR: if defined, forces pageable data physical address. 184# CFG_NS_ENTRY_ADDR: if defined, forces NS World physical entry address. 185# CFG_DT_ADDR: if defined, forces Device Tree data physical address. 186endif 187 188# CFG_MAX_CACHE_LINE_SHIFT is used to define platform specific maximum cache 189# line size in address lines. This must cover all inner and outer cache levels. 190# When data is aligned with this and cache operations are performed then those 191# only affect correct data. 192# 193# Default value (6 lines or 64 bytes) should cover most architectures, override 194# this in platform config if different. 195CFG_MAX_CACHE_LINE_SHIFT ?= 6 196 197core-platform-cppflags += -I$(arch-dir)/include 198core-platform-subdirs += \ 199 $(addprefix $(arch-dir)/, kernel crypto mm tee) $(platform-dir) 200 201ifneq ($(CFG_WITH_ARM_TRUSTED_FW),y) 202core-platform-subdirs += $(arch-dir)/sm 203endif 204 205arm64-platform-cppflags += -DARM64=1 -D__LP64__=1 206arm32-platform-cppflags += -DARM32=1 -D__ILP32__=1 207 208platform-cflags-generic ?= -ffunction-sections -fdata-sections -pipe 209platform-aflags-generic ?= -pipe 210 211arm32-platform-aflags += -marm 212 213arm32-platform-cflags-no-hard-float ?= -mfloat-abi=soft 214arm32-platform-cflags-hard-float ?= -mfloat-abi=hard -funsafe-math-optimizations 215arm32-platform-cflags-generic-thumb ?= -mthumb \ 216 -fno-short-enums -fno-common -mno-unaligned-access 217arm32-platform-cflags-generic-arm ?= -marm -fno-omit-frame-pointer -mapcs \ 218 -fno-short-enums -fno-common -mno-unaligned-access 219arm32-platform-aflags-no-hard-float ?= 220 221arm64-platform-cflags-no-hard-float ?= -mgeneral-regs-only 222arm64-platform-cflags-hard-float ?= 223arm64-platform-cflags-generic := -mstrict-align $(call cc-option,-mno-outline-atomics,) 224 225ifeq ($(CFG_MEMTAG),y) 226arm64-platform-cflags += -march=armv8.5-a+memtag 227arm64-platform-aflags += -march=armv8.5-a+memtag 228endif 229 230platform-cflags-optimization ?= -O$(CFG_CC_OPT_LEVEL) 231 232ifeq ($(CFG_DEBUG_INFO),y) 233platform-cflags-debug-info ?= -g3 234platform-aflags-debug-info ?= -g 235endif 236 237core-platform-cflags += $(platform-cflags-optimization) 238core-platform-cflags += $(platform-cflags-generic) 239core-platform-cflags += $(platform-cflags-debug-info) 240 241core-platform-aflags += $(platform-aflags-generic) 242core-platform-aflags += $(platform-aflags-debug-info) 243 244ifeq ($(call cfg-one-enabled, CFG_CORE_ASLR CFG_CORE_PHYS_RELOCATABLE),y) 245core-platform-cflags += -fpie 246endif 247 248ifeq ($(CFG_CORE_PAUTH),y) 249bp-core-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf) 250endif 251 252ifeq ($(CFG_CORE_BTI),y) 253bp-core-opt := $(call cc-option,-mbranch-protection=bti) 254endif 255 256ifeq (y-y,$(CFG_CORE_PAUTH)-$(CFG_CORE_BTI)) 257bp-core-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf+bti) 258endif 259 260ifeq (y,$(filter $(CFG_CORE_BTI) $(CFG_CORE_PAUTH),y)) 261ifeq (,$(bp-core-opt)) 262$(error -mbranch-protection not supported) 263endif 264core-platform-cflags += $(bp-core-opt) 265endif 266 267ifeq ($(CFG_ARM64_core),y) 268core-platform-cppflags += $(arm64-platform-cppflags) 269core-platform-cflags += $(arm64-platform-cflags) 270core-platform-cflags += $(arm64-platform-cflags-generic) 271core-platform-cflags += $(arm64-platform-cflags-no-hard-float) 272core-platform-aflags += $(arm64-platform-aflags) 273else 274core-platform-cppflags += $(arm32-platform-cppflags) 275core-platform-cflags += $(arm32-platform-cflags) 276core-platform-cflags += $(arm32-platform-cflags-no-hard-float) 277ifeq ($(CFG_UNWIND),y) 278core-platform-cflags += -funwind-tables 279endif 280ifeq ($(CFG_SYSCALL_FTRACE),y) 281core-platform-cflags += $(arm32-platform-cflags-generic-arm) 282else 283core-platform-cflags += $(arm32-platform-cflags-generic-thumb) 284endif 285core-platform-aflags += $(core_arm32-platform-aflags) 286core-platform-aflags += $(arm32-platform-aflags) 287endif 288 289# Provide default supported-ta-targets if not set by the platform config 290ifeq (,$(supported-ta-targets)) 291supported-ta-targets = ta_arm32 292ifeq ($(CFG_ARM64_core),y) 293supported-ta-targets += ta_arm64 294endif 295endif 296 297ta-targets := $(if $(CFG_USER_TA_TARGETS),$(filter $(supported-ta-targets),$(CFG_USER_TA_TARGETS)),$(supported-ta-targets)) 298unsup-targets := $(filter-out $(ta-targets),$(CFG_USER_TA_TARGETS)) 299ifneq (,$(unsup-targets)) 300$(error CFG_USER_TA_TARGETS contains unsupported value(s): $(unsup-targets). Valid values: $(supported-ta-targets)) 301endif 302 303ifneq ($(filter ta_arm32,$(ta-targets)),) 304# Variables for ta-target/sm "ta_arm32" 305CFG_ARM32_ta_arm32 := y 306arch-bits-ta_arm32 := 32 307ta_arm32-platform-cppflags += $(arm32-platform-cppflags) 308ta_arm32-platform-cflags += $(arm32-platform-cflags) 309ta_arm32-platform-cflags += $(platform-cflags-optimization) 310ta_arm32-platform-cflags += $(platform-cflags-debug-info) 311ta_arm32-platform-cflags += -fpic 312 313# Thumb mode doesn't support function graph tracing due to missing 314# frame pointer support required to trace function call chain. So 315# rather compile in ARM mode if function tracing is enabled. 316ifeq ($(CFG_FTRACE_SUPPORT),y) 317ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-arm) 318else 319ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-thumb) 320endif 321 322ifeq ($(arm32-platform-hard-float-enabled),y) 323ta_arm32-platform-cflags += $(arm32-platform-cflags-hard-float) 324else 325ta_arm32-platform-cflags += $(arm32-platform-cflags-no-hard-float) 326endif 327ifeq ($(CFG_UNWIND),y) 328ta_arm32-platform-cflags += -funwind-tables 329endif 330ta_arm32-platform-aflags += $(platform-aflags-generic) 331ta_arm32-platform-aflags += $(platform-aflags-debug-info) 332ta_arm32-platform-aflags += $(arm32-platform-aflags) 333 334ta_arm32-platform-cxxflags += -fpic 335ta_arm32-platform-cxxflags += $(arm32-platform-cxxflags) 336ta_arm32-platform-cxxflags += $(platform-cflags-optimization) 337ta_arm32-platform-cxxflags += $(platform-cflags-debug-info) 338 339ifeq ($(arm32-platform-hard-float-enabled),y) 340ta_arm32-platform-cxxflags += $(arm32-platform-cflags-hard-float) 341else 342ta_arm32-platform-cxxflags += $(arm32-platform-cflags-no-hard-float) 343endif 344 345ta-mk-file-export-vars-ta_arm32 += CFG_ARM32_ta_arm32 346ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cppflags 347ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cflags 348ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-aflags 349ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cxxflags 350 351ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE ?= arm-linux-gnueabihf-_nl_ 352ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE32 ?= $$(CROSS_COMPILE)_nl_ 353ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE_ta_arm32 ?= $$(CROSS_COMPILE32)_nl_ 354ta-mk-file-export-add-ta_arm32 += COMPILER ?= gcc_nl_ 355ta-mk-file-export-add-ta_arm32 += COMPILER_ta_arm32 ?= $$(COMPILER)_nl_ 356ta-mk-file-export-add-ta_arm32 += PYTHON3 ?= python3_nl_ 357endif 358 359ifneq ($(filter ta_arm64,$(ta-targets)),) 360# Variables for ta-target/sm "ta_arm64" 361CFG_ARM64_ta_arm64 := y 362arch-bits-ta_arm64 := 64 363ta_arm64-platform-cppflags += $(arm64-platform-cppflags) 364ta_arm64-platform-cflags += $(arm64-platform-cflags) 365ta_arm64-platform-cflags += $(platform-cflags-optimization) 366ta_arm64-platform-cflags += $(platform-cflags-debug-info) 367ta_arm64-platform-cflags += -fpic 368ta_arm64-platform-cflags += $(arm64-platform-cflags-generic) 369ifeq ($(arm64-platform-hard-float-enabled),y) 370ta_arm64-platform-cflags += $(arm64-platform-cflags-hard-float) 371else 372ta_arm64-platform-cflags += $(arm64-platform-cflags-no-hard-float) 373endif 374ta_arm64-platform-aflags += $(platform-aflags-generic) 375ta_arm64-platform-aflags += $(platform-aflags-debug-info) 376ta_arm64-platform-aflags += $(arm64-platform-aflags) 377 378ta_arm64-platform-cxxflags += -fpic 379ta_arm64-platform-cxxflags += $(platform-cflags-optimization) 380ta_arm64-platform-cxxflags += $(platform-cflags-debug-info) 381 382ifeq ($(CFG_TA_PAUTH),y) 383bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf) 384endif 385 386ifeq ($(CFG_TA_BTI),y) 387bp-ta-opt := $(call cc-option,-mbranch-protection=bti) 388endif 389 390ifeq (y-y,$(CFG_TA_PAUTH)-$(CFG_TA_BTI)) 391bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf+bti) 392endif 393 394ifeq (y,$(filter $(CFG_TA_BTI) $(CFG_TA_PAUTH),y)) 395ifeq (,$(bp-ta-opt)) 396$(error -mbranch-protection not supported) 397endif 398ta_arm64-platform-cflags += $(bp-ta-opt) 399endif 400 401ta-mk-file-export-vars-ta_arm64 += CFG_ARM64_ta_arm64 402ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cppflags 403ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cflags 404ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-aflags 405ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cxxflags 406 407ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE64 ?= $$(CROSS_COMPILE)_nl_ 408ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE_ta_arm64 ?= $$(CROSS_COMPILE64)_nl_ 409ta-mk-file-export-add-ta_arm64 += COMPILER ?= gcc_nl_ 410ta-mk-file-export-add-ta_arm64 += COMPILER_ta_arm64 ?= $$(COMPILER)_nl_ 411ta-mk-file-export-add-ta_arm64 += PYTHON3 ?= python3_nl_ 412endif 413 414# Set cross compiler prefix for each TA target 415$(foreach sm, $(ta-targets), $(eval CROSS_COMPILE_$(sm) ?= $(CROSS_COMPILE$(arch-bits-$(sm))))) 416 417arm32-sysreg-txt = core/arch/arm/kernel/arm32_sysreg.txt 418arm32-sysregs-$(arm32-sysreg-txt)-h := arm32_sysreg.h 419arm32-sysregs-$(arm32-sysreg-txt)-s := arm32_sysreg.S 420arm32-sysregs += $(arm32-sysreg-txt) 421 422ifeq ($(CFG_ARM_GICV3),y) 423arm32-gicv3-sysreg-txt = core/arch/arm/kernel/arm32_gicv3_sysreg.txt 424arm32-sysregs-$(arm32-gicv3-sysreg-txt)-h := arm32_gicv3_sysreg.h 425arm32-sysregs-$(arm32-gicv3-sysreg-txt)-s := arm32_gicv3_sysreg.S 426arm32-sysregs += $(arm32-gicv3-sysreg-txt) 427endif 428 429arm32-sysregs-out := $(out-dir)/$(sm)/include/generated 430 431define process-arm32-sysreg 432FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 433cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 434 435$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h): $(1) scripts/arm32_sysreg.py 436 @$(cmd-echo-silent) ' GEN $$@' 437 $(q)mkdir -p $$(dir $$@) 438 $(q)scripts/arm32_sysreg.py --guard __$$(arm32-sysregs-$(1)-h) \ 439 < $$< > $$@ 440 441FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 442cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 443 444$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s): $(1) scripts/arm32_sysreg.py 445 @$(cmd-echo-silent) ' GEN $$@' 446 $(q)mkdir -p $$(dir $$@) 447 $(q)scripts/arm32_sysreg.py --s_file < $$< > $$@ 448endef #process-arm32-sysreg 449 450$(foreach sr, $(arm32-sysregs), $(eval $(call process-arm32-sysreg,$(sr)))) 451