1# Setup compiler for the core module 2ifeq ($(CFG_ARM64_core),y) 3arch-bits-core := 64 4else 5arch-bits-core := 32 6endif 7CROSS_COMPILE_core := $(CROSS_COMPILE$(arch-bits-core)) 8COMPILER_core := $(COMPILER) 9include mk/$(COMPILER_core).mk 10 11# Defines the cc-option macro using the compiler set for the core module 12include mk/cc-option.mk 13 14# Size of emulated TrustZone protected SRAM, 448 kB. 15# Only applicable when paging is enabled. 16CFG_CORE_TZSRAM_EMUL_SIZE ?= 458752 17 18ifneq ($(CFG_LPAE_ADDR_SPACE_SIZE),) 19$(warning Error: CFG_LPAE_ADDR_SPACE_SIZE is not supported any longer) 20$(error Error: Please use CFG_LPAE_ADDR_SPACE_BITS instead) 21endif 22 23CFG_LPAE_ADDR_SPACE_BITS ?= 32 24 25CFG_MMAP_REGIONS ?= 13 26CFG_RESERVED_VASPACE_SIZE ?= (1024 * 1024 * 10) 27 28ifeq ($(CFG_ARM64_core),y) 29ifeq ($(CFG_ARM32_core),y) 30$(error CFG_ARM64_core and CFG_ARM32_core cannot be both 'y') 31endif 32CFG_KERN_LINKER_FORMAT ?= elf64-littleaarch64 33CFG_KERN_LINKER_ARCH ?= aarch64 34# TCR_EL1.IPS needs to be initialized according to the largest physical 35# address that we need to map. 36# Physical address size 37# 32 bits, 4GB. 38# 36 bits, 64GB. 39# (etc.) 40CFG_CORE_ARM64_PA_BITS ?= 32 41$(call force,CFG_WITH_LPAE,y) 42else 43$(call force,CFG_ARM32_core,y) 44CFG_KERN_LINKER_FORMAT ?= elf32-littlearm 45CFG_KERN_LINKER_ARCH ?= arm 46endif 47 48ifeq ($(CFG_TA_FLOAT_SUPPORT),y) 49# Use hard-float for floating point support in user TAs instead of 50# soft-float 51CFG_WITH_VFP ?= y 52ifeq ($(CFG_ARM64_core),y) 53# AArch64 has no fallback to soft-float 54$(call force,CFG_WITH_VFP,y) 55endif 56ifeq ($(CFG_WITH_VFP),y) 57arm64-platform-hard-float-enabled := y 58ifneq ($(CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT),y) 59arm32-platform-hard-float-enabled := y 60endif 61endif 62endif 63 64# Adds protection against CVE-2017-5715 also know as Spectre 65# (https://spectreattack.com) 66# See also https://developer.arm.com/-/media/Files/pdf/Cache_Speculation_Side-channels.pdf 67# Variant 2 68CFG_CORE_WORKAROUND_SPECTRE_BP ?= y 69# Same as CFG_CORE_WORKAROUND_SPECTRE_BP but targeting exceptions from 70# secure EL0 instead of non-secure world, including mitigation for 71# CVE-2022-23960. 72CFG_CORE_WORKAROUND_SPECTRE_BP_SEC ?= $(CFG_CORE_WORKAROUND_SPECTRE_BP) 73 74# Adds protection against a tool like Cachegrab 75# (https://github.com/nccgroup/cachegrab), which uses non-secure interrupts 76# to prime and later analyze the L1D, L1I and BTB caches to gain 77# information from secure world execution. 78CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME ?= y 79ifeq ($(CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME),y) 80$(call force,CFG_CORE_WORKAROUND_SPECTRE_BP,y,Required by CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME) 81endif 82 83CFG_CORE_RWDATA_NOEXEC ?= y 84CFG_CORE_RODATA_NOEXEC ?= n 85ifeq ($(CFG_CORE_RODATA_NOEXEC),y) 86$(call force,CFG_CORE_RWDATA_NOEXEC,y) 87endif 88# 'y' to set the Alignment Check Enable bit in SCTLR/SCTLR_EL1, 'n' to clear it 89CFG_SCTLR_ALIGNMENT_CHECK ?= n 90 91ifeq ($(CFG_CORE_LARGE_PHYS_ADDR),y) 92$(call force,CFG_WITH_LPAE,y) 93endif 94 95# SPMC configuration "S-EL1 SPMC" where SPM Core is implemented at S-EL1, 96# that is, OP-TEE. 97ifeq ($(CFG_CORE_SEL1_SPMC),y) 98$(call force,CFG_CORE_FFA,y) 99$(call force,CFG_CORE_SEL2_SPMC,n) 100$(call force,CFG_CORE_EL3_SPMC,n) 101endif 102# SPMC configuration "S-EL2 SPMC" where SPM Core is implemented at S-EL2, 103# that is, the hypervisor sandboxing OP-TEE 104ifeq ($(CFG_CORE_SEL2_SPMC),y) 105$(call force,CFG_CORE_FFA,y) 106$(call force,CFG_CORE_SEL1_SPMC,n) 107$(call force,CFG_CORE_EL3_SPMC,n) 108endif 109# SPMC configuration "EL3 SPMC" where SPM Core is implemented at EL3, that 110# is, in TF-A 111ifeq ($(CFG_CORE_EL3_SPMC),y) 112$(call force,CFG_CORE_FFA,y) 113$(call force,CFG_CORE_SEL2_SPMC,n) 114$(call force,CFG_CORE_SEL1_SPMC,n) 115endif 116 117# Unmaps all kernel mode code except the code needed to take exceptions 118# from user space and restore kernel mode mapping again. This gives more 119# strict control over what is accessible while in user mode. 120# Addresses CVE-2017-5715 (aka Meltdown) known to affect Arm Cortex-A75 121CFG_CORE_UNMAP_CORE_AT_EL0 ?= y 122 123# Initialize PMCR.DP to 1 to prohibit cycle counting in secure state, and 124# save/restore PMCR during world switch. 125CFG_SM_NO_CYCLE_COUNTING ?= y 126 127 128# CFG_CORE_ASYNC_NOTIF_GIC_INTID is defined by the platform to some free 129# interrupt. Setting it to a non-zero number enables support for using an 130# Arm-GIC to notify normal world. This config variable should use a value 131# larger the 32 to make it of the type SPI. 132# Note that asynchronous notifactions must be enabled with 133# CFG_CORE_ASYNC_NOTIF=y for this variable to be used. 134CFG_CORE_ASYNC_NOTIF_GIC_INTID ?= 0 135 136ifeq ($(CFG_ARM32_core),y) 137# Configration directive related to ARMv7 optee boot arguments. 138# CFG_PAGEABLE_ADDR: if defined, forces pageable data physical address. 139# CFG_NS_ENTRY_ADDR: if defined, forces NS World physical entry address. 140# CFG_DT_ADDR: if defined, forces Device Tree data physical address. 141endif 142 143core-platform-cppflags += -I$(arch-dir)/include 144core-platform-subdirs += \ 145 $(addprefix $(arch-dir)/, kernel crypto mm tee) $(platform-dir) 146 147ifneq ($(CFG_WITH_ARM_TRUSTED_FW),y) 148core-platform-subdirs += $(arch-dir)/sm 149endif 150 151arm64-platform-cppflags += -DARM64=1 -D__LP64__=1 152arm32-platform-cppflags += -DARM32=1 -D__ILP32__=1 153 154platform-cflags-generic ?= -ffunction-sections -fdata-sections -pipe 155platform-aflags-generic ?= -pipe 156 157arm32-platform-aflags += -marm 158 159arm32-platform-cflags-no-hard-float ?= -mfloat-abi=soft 160arm32-platform-cflags-hard-float ?= -mfloat-abi=hard -funsafe-math-optimizations 161arm32-platform-cflags-generic-thumb ?= -mthumb \ 162 -fno-short-enums -fno-common -mno-unaligned-access 163arm32-platform-cflags-generic-arm ?= -marm -fno-omit-frame-pointer -mapcs \ 164 -fno-short-enums -fno-common -mno-unaligned-access 165arm32-platform-aflags-no-hard-float ?= 166 167arm64-platform-cflags-no-hard-float ?= -mgeneral-regs-only 168arm64-platform-cflags-hard-float ?= 169arm64-platform-cflags-generic := -mstrict-align $(call cc-option,-mno-outline-atomics,) 170 171ifeq ($(CFG_MEMTAG),y) 172arm64-platform-cflags += -march=armv8.5-a+memtag 173arm64-platform-aflags += -march=armv8.5-a+memtag 174endif 175 176platform-cflags-optimization ?= -O$(CFG_CC_OPT_LEVEL) 177 178ifeq ($(CFG_DEBUG_INFO),y) 179platform-cflags-debug-info ?= -g3 180platform-aflags-debug-info ?= -g 181endif 182 183core-platform-cflags += $(platform-cflags-optimization) 184core-platform-cflags += $(platform-cflags-generic) 185core-platform-cflags += $(platform-cflags-debug-info) 186 187core-platform-aflags += $(platform-aflags-generic) 188core-platform-aflags += $(platform-aflags-debug-info) 189 190ifeq ($(CFG_CORE_ASLR),y) 191core-platform-cflags += -fpie 192endif 193 194ifeq ($(CFG_CORE_BTI),y) 195bti-opt := $(call cc-option,-mbranch-protection=bti) 196ifeq (,$(bti-opt)) 197$(error -mbranch-protection=bti not supported) 198endif 199core-platform-cflags += $(bti-opt) 200endif 201 202ifeq ($(CFG_ARM64_core),y) 203core-platform-cppflags += $(arm64-platform-cppflags) 204core-platform-cflags += $(arm64-platform-cflags) 205core-platform-cflags += $(arm64-platform-cflags-generic) 206core-platform-cflags += $(arm64-platform-cflags-no-hard-float) 207core-platform-aflags += $(arm64-platform-aflags) 208else 209core-platform-cppflags += $(arm32-platform-cppflags) 210core-platform-cflags += $(arm32-platform-cflags) 211core-platform-cflags += $(arm32-platform-cflags-no-hard-float) 212ifeq ($(CFG_UNWIND),y) 213core-platform-cflags += -funwind-tables 214endif 215ifeq ($(CFG_SYSCALL_FTRACE),y) 216core-platform-cflags += $(arm32-platform-cflags-generic-arm) 217else 218core-platform-cflags += $(arm32-platform-cflags-generic-thumb) 219endif 220core-platform-aflags += $(core_arm32-platform-aflags) 221core-platform-aflags += $(arm32-platform-aflags) 222endif 223 224# Provide default supported-ta-targets if not set by the platform config 225ifeq (,$(supported-ta-targets)) 226supported-ta-targets = ta_arm32 227ifeq ($(CFG_ARM64_core),y) 228supported-ta-targets += ta_arm64 229endif 230endif 231 232ta-targets := $(if $(CFG_USER_TA_TARGETS),$(filter $(supported-ta-targets),$(CFG_USER_TA_TARGETS)),$(supported-ta-targets)) 233unsup-targets := $(filter-out $(ta-targets),$(CFG_USER_TA_TARGETS)) 234ifneq (,$(unsup-targets)) 235$(error CFG_USER_TA_TARGETS contains unsupported value(s): $(unsup-targets). Valid values: $(supported-ta-targets)) 236endif 237 238ifneq ($(filter ta_arm32,$(ta-targets)),) 239# Variables for ta-target/sm "ta_arm32" 240CFG_ARM32_ta_arm32 := y 241arch-bits-ta_arm32 := 32 242ta_arm32-platform-cppflags += $(arm32-platform-cppflags) 243ta_arm32-platform-cflags += $(arm32-platform-cflags) 244ta_arm32-platform-cflags += $(platform-cflags-optimization) 245ta_arm32-platform-cflags += $(platform-cflags-debug-info) 246ta_arm32-platform-cflags += -fpic 247 248# Thumb mode doesn't support function graph tracing due to missing 249# frame pointer support required to trace function call chain. So 250# rather compile in ARM mode if function tracing is enabled. 251ifeq ($(CFG_FTRACE_SUPPORT),y) 252ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-arm) 253else 254ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-thumb) 255endif 256 257ifeq ($(arm32-platform-hard-float-enabled),y) 258ta_arm32-platform-cflags += $(arm32-platform-cflags-hard-float) 259else 260ta_arm32-platform-cflags += $(arm32-platform-cflags-no-hard-float) 261endif 262ifeq ($(CFG_UNWIND),y) 263ta_arm32-platform-cflags += -funwind-tables 264endif 265ta_arm32-platform-aflags += $(platform-aflags-generic) 266ta_arm32-platform-aflags += $(platform-aflags-debug-info) 267ta_arm32-platform-aflags += $(arm32-platform-aflags) 268 269ta_arm32-platform-cxxflags += -fpic 270ta_arm32-platform-cxxflags += $(arm32-platform-cxxflags) 271ta_arm32-platform-cxxflags += $(platform-cflags-optimization) 272ta_arm32-platform-cxxflags += $(platform-cflags-debug-info) 273 274ifeq ($(arm32-platform-hard-float-enabled),y) 275ta_arm32-platform-cxxflags += $(arm32-platform-cflags-hard-float) 276else 277ta_arm32-platform-cxxflags += $(arm32-platform-cflags-no-hard-float) 278endif 279 280ta-mk-file-export-vars-ta_arm32 += CFG_ARM32_ta_arm32 281ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cppflags 282ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cflags 283ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-aflags 284ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cxxflags 285 286ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE ?= arm-linux-gnueabihf-_nl_ 287ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE32 ?= $$(CROSS_COMPILE)_nl_ 288ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE_ta_arm32 ?= $$(CROSS_COMPILE32)_nl_ 289ta-mk-file-export-add-ta_arm32 += COMPILER ?= gcc_nl_ 290ta-mk-file-export-add-ta_arm32 += COMPILER_ta_arm32 ?= $$(COMPILER)_nl_ 291ta-mk-file-export-add-ta_arm32 += PYTHON3 ?= python3_nl_ 292endif 293 294ifneq ($(filter ta_arm64,$(ta-targets)),) 295# Variables for ta-target/sm "ta_arm64" 296CFG_ARM64_ta_arm64 := y 297arch-bits-ta_arm64 := 64 298ta_arm64-platform-cppflags += $(arm64-platform-cppflags) 299ta_arm64-platform-cflags += $(arm64-platform-cflags) 300ta_arm64-platform-cflags += $(platform-cflags-optimization) 301ta_arm64-platform-cflags += $(platform-cflags-debug-info) 302ta_arm64-platform-cflags += -fpic 303ta_arm64-platform-cflags += $(arm64-platform-cflags-generic) 304ifeq ($(arm64-platform-hard-float-enabled),y) 305ta_arm64-platform-cflags += $(arm64-platform-cflags-hard-float) 306else 307ta_arm64-platform-cflags += $(arm64-platform-cflags-no-hard-float) 308endif 309ta_arm64-platform-aflags += $(platform-aflags-generic) 310ta_arm64-platform-aflags += $(platform-aflags-debug-info) 311ta_arm64-platform-aflags += $(arm64-platform-aflags) 312 313ta_arm64-platform-cxxflags += -fpic 314ta_arm64-platform-cxxflags += $(platform-cflags-optimization) 315ta_arm64-platform-cxxflags += $(platform-cflags-debug-info) 316 317ifeq ($(CFG_TA_PAUTH),y) 318bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf) 319endif 320 321ifeq ($(CFG_TA_BTI),y) 322bp-ta-opt := $(call cc-option,-mbranch-protection=bti) 323endif 324 325ifeq (y-y,$(CFG_TA_PAUTH)-$(CFG_TA_BTI)) 326bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf+bti) 327endif 328 329ifeq (y,$(filter $(CFG_TA_BTI) $(CFG_TA_PAUTH),y)) 330ifeq (,$(bp-ta-opt)) 331$(error -mbranch-protection not supported) 332endif 333ta_arm64-platform-cflags += $(bp-ta-opt) 334endif 335 336ta-mk-file-export-vars-ta_arm64 += CFG_ARM64_ta_arm64 337ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cppflags 338ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cflags 339ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-aflags 340ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cxxflags 341 342ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE64 ?= $$(CROSS_COMPILE)_nl_ 343ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE_ta_arm64 ?= $$(CROSS_COMPILE64)_nl_ 344ta-mk-file-export-add-ta_arm64 += COMPILER ?= gcc_nl_ 345ta-mk-file-export-add-ta_arm64 += COMPILER_ta_arm64 ?= $$(COMPILER)_nl_ 346ta-mk-file-export-add-ta_arm64 += PYTHON3 ?= python3_nl_ 347endif 348 349# Set cross compiler prefix for each TA target 350$(foreach sm, $(ta-targets), $(eval CROSS_COMPILE_$(sm) ?= $(CROSS_COMPILE$(arch-bits-$(sm))))) 351 352arm32-sysreg-txt = core/arch/arm/kernel/arm32_sysreg.txt 353arm32-sysregs-$(arm32-sysreg-txt)-h := arm32_sysreg.h 354arm32-sysregs-$(arm32-sysreg-txt)-s := arm32_sysreg.S 355arm32-sysregs += $(arm32-sysreg-txt) 356 357ifeq ($(CFG_ARM_GICV3),y) 358arm32-gicv3-sysreg-txt = core/arch/arm/kernel/arm32_gicv3_sysreg.txt 359arm32-sysregs-$(arm32-gicv3-sysreg-txt)-h := arm32_gicv3_sysreg.h 360arm32-sysregs-$(arm32-gicv3-sysreg-txt)-s := arm32_gicv3_sysreg.S 361arm32-sysregs += $(arm32-gicv3-sysreg-txt) 362endif 363 364arm32-sysregs-out := $(out-dir)/$(sm)/include/generated 365 366define process-arm32-sysreg 367FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 368cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 369 370$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h): $(1) scripts/arm32_sysreg.py 371 @$(cmd-echo-silent) ' GEN $$@' 372 $(q)mkdir -p $$(dir $$@) 373 $(q)scripts/arm32_sysreg.py --guard __$$(arm32-sysregs-$(1)-h) \ 374 < $$< > $$@ 375 376FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 377cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 378 379$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s): $(1) scripts/arm32_sysreg.py 380 @$(cmd-echo-silent) ' GEN $$@' 381 $(q)mkdir -p $$(dir $$@) 382 $(q)scripts/arm32_sysreg.py --s_file < $$< > $$@ 383endef #process-arm32-sysreg 384 385$(foreach sr, $(arm32-sysregs), $(eval $(call process-arm32-sysreg,$(sr)))) 386