1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2011 3*4882a593Smuzhiyun * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Vased on: 6*4882a593Smuzhiyun * (C) Copyright 2009 7*4882a593Smuzhiyun * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _UBLIMAGE_H_ 13*4882a593Smuzhiyun #define _UBLIMAGE_H_ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun enum ublimage_cmd { 16*4882a593Smuzhiyun CMD_INVALID, 17*4882a593Smuzhiyun CMD_BOOT_MODE, 18*4882a593Smuzhiyun CMD_ENTRY, 19*4882a593Smuzhiyun CMD_PAGE, 20*4882a593Smuzhiyun CMD_ST_BLOCK, 21*4882a593Smuzhiyun CMD_ST_PAGE, 22*4882a593Smuzhiyun CMD_LD_ADDR 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun enum ublimage_fld_types { 26*4882a593Smuzhiyun CFG_INVALID = -1, 27*4882a593Smuzhiyun CFG_COMMAND, 28*4882a593Smuzhiyun CFG_REG_VALUE 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * from sprufg5a.pdf Table 110 33*4882a593Smuzhiyun * Used by RBL when doing NAND boot 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun #define UBL_MAGIC_BASE (0xA1ACED00) 36*4882a593Smuzhiyun /* Safe boot mode */ 37*4882a593Smuzhiyun #define UBL_MAGIC_SAFE (0x00) 38*4882a593Smuzhiyun /* DMA boot mode */ 39*4882a593Smuzhiyun #define UBL_MAGIC_DMA (0x11) 40*4882a593Smuzhiyun /* I Cache boot mode */ 41*4882a593Smuzhiyun #define UBL_MAGIC_IC (0x22) 42*4882a593Smuzhiyun /* Fast EMIF boot mode */ 43*4882a593Smuzhiyun #define UBL_MAGIC_FAST (0x33) 44*4882a593Smuzhiyun /* DMA + ICache boot mode */ 45*4882a593Smuzhiyun #define UBL_MAGIC_DMA_IC (0x44) 46*4882a593Smuzhiyun /* DMA + ICache + Fast EMIF boot mode */ 47*4882a593Smuzhiyun #define UBL_MAGIC_DMA_IC_FAST (0x55) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Define max UBL image size */ 50*4882a593Smuzhiyun #define UBL_IMAGE_SIZE (0x00003800u) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* one NAND block */ 53*4882a593Smuzhiyun #define UBL_BLOCK_SIZE 2048 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* from sprufg5a.pdf Table 109 */ 56*4882a593Smuzhiyun struct ubl_header { 57*4882a593Smuzhiyun uint32_t magic; /* Magic Number, see UBL_* defines */ 58*4882a593Smuzhiyun uint32_t entry; /* entry point address for bootloader */ 59*4882a593Smuzhiyun uint32_t pages; /* number of pages (size of bootloader) */ 60*4882a593Smuzhiyun uint32_t block; /* 61*4882a593Smuzhiyun * blocknumber where user bootloader is 62*4882a593Smuzhiyun * present 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun uint32_t page; /* 65*4882a593Smuzhiyun * page number where user bootloader is 66*4882a593Smuzhiyun * present. 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun uint32_t pll_m; /* 69*4882a593Smuzhiyun * PLL setting -Multiplier (only valid if 70*4882a593Smuzhiyun * Magic Number indicates PLL enable). 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun uint32_t pll_n; /* 73*4882a593Smuzhiyun * PLL setting -Divider (only valid if 74*4882a593Smuzhiyun * Magic Number indicates PLL enable). 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun uint32_t emif; /* 77*4882a593Smuzhiyun * fast EMIF setting (only valid if 78*4882a593Smuzhiyun * Magic Number indicates fast EMIF boot). 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun /* to fit in one nand block */ 81*4882a593Smuzhiyun unsigned char res[UBL_BLOCK_SIZE - 8 * 4]; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #endif /* _UBLIMAGE_H_ */ 85