1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2002
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /*
11*4882a593Smuzhiyun * CPU test
12*4882a593Smuzhiyun * Binary instructions instr rA,rS
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * Logic instructions: cntlzw
15*4882a593Smuzhiyun * Arithmetic instructions: extsb, extsh
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun * The test contains a pre-built table of instructions, operands and
18*4882a593Smuzhiyun * expected results. For each table entry, the test will cyclically use
19*4882a593Smuzhiyun * different sets of operand registers and result registers.
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <post.h>
23*4882a593Smuzhiyun #include "cpu_asm.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #if CONFIG_POST & CONFIG_SYS_POST_CPU
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
28*4882a593Smuzhiyun extern ulong cpu_post_makecr (long v);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static struct cpu_post_twox_s
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun ulong cmd;
33*4882a593Smuzhiyun ulong op;
34*4882a593Smuzhiyun ulong res;
35*4882a593Smuzhiyun } cpu_post_twox_table[] =
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun OP_EXTSB,
39*4882a593Smuzhiyun 3,
40*4882a593Smuzhiyun 3
41*4882a593Smuzhiyun },
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun OP_EXTSB,
44*4882a593Smuzhiyun 0xff,
45*4882a593Smuzhiyun -1
46*4882a593Smuzhiyun },
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun OP_EXTSH,
49*4882a593Smuzhiyun 3,
50*4882a593Smuzhiyun 3
51*4882a593Smuzhiyun },
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun OP_EXTSH,
54*4882a593Smuzhiyun 0xff,
55*4882a593Smuzhiyun 0xff
56*4882a593Smuzhiyun },
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun OP_EXTSH,
59*4882a593Smuzhiyun 0xffff,
60*4882a593Smuzhiyun -1
61*4882a593Smuzhiyun },
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun OP_CNTLZW,
64*4882a593Smuzhiyun 0x000fffff,
65*4882a593Smuzhiyun 12
66*4882a593Smuzhiyun },
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun static unsigned int cpu_post_twox_size = ARRAY_SIZE(cpu_post_twox_table);
69*4882a593Smuzhiyun
cpu_post_test_twox(void)70*4882a593Smuzhiyun int cpu_post_test_twox (void)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun int ret = 0;
73*4882a593Smuzhiyun unsigned int i, reg;
74*4882a593Smuzhiyun int flag = disable_interrupts();
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun for (i = 0; i < cpu_post_twox_size && ret == 0; i++)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun struct cpu_post_twox_s *test = cpu_post_twox_table + i;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun for (reg = 0; reg < 32 && ret == 0; reg++)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun unsigned int reg0 = (reg + 0) % 32;
83*4882a593Smuzhiyun unsigned int reg1 = (reg + 1) % 32;
84*4882a593Smuzhiyun unsigned int stk = reg < 16 ? 31 : 15;
85*4882a593Smuzhiyun unsigned long code[] =
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun ASM_STW(stk, 1, -4),
88*4882a593Smuzhiyun ASM_ADDI(stk, 1, -16),
89*4882a593Smuzhiyun ASM_STW(3, stk, 8),
90*4882a593Smuzhiyun ASM_STW(reg0, stk, 4),
91*4882a593Smuzhiyun ASM_STW(reg1, stk, 0),
92*4882a593Smuzhiyun ASM_LWZ(reg0, stk, 8),
93*4882a593Smuzhiyun ASM_11X(test->cmd, reg1, reg0),
94*4882a593Smuzhiyun ASM_STW(reg1, stk, 8),
95*4882a593Smuzhiyun ASM_LWZ(reg1, stk, 0),
96*4882a593Smuzhiyun ASM_LWZ(reg0, stk, 4),
97*4882a593Smuzhiyun ASM_LWZ(3, stk, 8),
98*4882a593Smuzhiyun ASM_ADDI(1, stk, 16),
99*4882a593Smuzhiyun ASM_LWZ(stk, 1, -4),
100*4882a593Smuzhiyun ASM_BLR,
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun unsigned long codecr[] =
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun ASM_STW(stk, 1, -4),
105*4882a593Smuzhiyun ASM_ADDI(stk, 1, -16),
106*4882a593Smuzhiyun ASM_STW(3, stk, 8),
107*4882a593Smuzhiyun ASM_STW(reg0, stk, 4),
108*4882a593Smuzhiyun ASM_STW(reg1, stk, 0),
109*4882a593Smuzhiyun ASM_LWZ(reg0, stk, 8),
110*4882a593Smuzhiyun ASM_11X(test->cmd, reg1, reg0) | BIT_C,
111*4882a593Smuzhiyun ASM_STW(reg1, stk, 8),
112*4882a593Smuzhiyun ASM_LWZ(reg1, stk, 0),
113*4882a593Smuzhiyun ASM_LWZ(reg0, stk, 4),
114*4882a593Smuzhiyun ASM_LWZ(3, stk, 8),
115*4882a593Smuzhiyun ASM_ADDI(1, stk, 16),
116*4882a593Smuzhiyun ASM_LWZ(stk, 1, -4),
117*4882a593Smuzhiyun ASM_BLR,
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun ulong res;
120*4882a593Smuzhiyun ulong cr;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun if (ret == 0)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun cr = 0;
125*4882a593Smuzhiyun cpu_post_exec_21 (code, & cr, & res, test->op);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun ret = res == test->res && cr == 0 ? 0 : -1;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun if (ret != 0)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun post_log ("Error at twox test %d !\n", i);
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun if (ret == 0)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun cpu_post_exec_21 (codecr, & cr, & res, test->op);
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun ret = res == test->res &&
140*4882a593Smuzhiyun (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun if (ret != 0)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun post_log ("Error at twox test %d !\n", i);
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun if (flag)
151*4882a593Smuzhiyun enable_interrupts();
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun return ret;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun #endif
157