xref: /OK3568_Linux_fs/u-boot/post/lib_powerpc/threei.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2002
3*4882a593Smuzhiyun  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /*
11*4882a593Smuzhiyun  * CPU test
12*4882a593Smuzhiyun  * Ternary instructions		instr rA,rS,UIMM
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * Logic instructions:		ori, oris, xori, xoris
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * The test contains a pre-built table of instructions, operands and
17*4882a593Smuzhiyun  * expected results. For each table entry, the test will cyclically use
18*4882a593Smuzhiyun  * different sets of operand registers and result registers.
19*4882a593Smuzhiyun  */
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include <post.h>
22*4882a593Smuzhiyun #include "cpu_asm.h"
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #if CONFIG_POST & CONFIG_SYS_POST_CPU
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
27*4882a593Smuzhiyun extern ulong cpu_post_makecr (long v);
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun static struct cpu_post_threei_s
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun     ulong cmd;
32*4882a593Smuzhiyun     ulong op1;
33*4882a593Smuzhiyun     ushort op2;
34*4882a593Smuzhiyun     ulong res;
35*4882a593Smuzhiyun } cpu_post_threei_table[] =
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun     {
38*4882a593Smuzhiyun 	OP_ORI,
39*4882a593Smuzhiyun 	0x80000000,
40*4882a593Smuzhiyun 	0xffff,
41*4882a593Smuzhiyun 	0x8000ffff
42*4882a593Smuzhiyun     },
43*4882a593Smuzhiyun     {
44*4882a593Smuzhiyun 	OP_ORIS,
45*4882a593Smuzhiyun 	0x00008000,
46*4882a593Smuzhiyun 	0xffff,
47*4882a593Smuzhiyun 	0xffff8000
48*4882a593Smuzhiyun     },
49*4882a593Smuzhiyun     {
50*4882a593Smuzhiyun 	OP_XORI,
51*4882a593Smuzhiyun 	0x8000ffff,
52*4882a593Smuzhiyun 	0xffff,
53*4882a593Smuzhiyun 	0x80000000
54*4882a593Smuzhiyun     },
55*4882a593Smuzhiyun     {
56*4882a593Smuzhiyun 	OP_XORIS,
57*4882a593Smuzhiyun 	0x00008000,
58*4882a593Smuzhiyun 	0xffff,
59*4882a593Smuzhiyun 	0xffff8000
60*4882a593Smuzhiyun     },
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table);
63*4882a593Smuzhiyun 
cpu_post_test_threei(void)64*4882a593Smuzhiyun int cpu_post_test_threei (void)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun     int ret = 0;
67*4882a593Smuzhiyun     unsigned int i, reg;
68*4882a593Smuzhiyun     int flag = disable_interrupts();
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun     for (i = 0; i < cpu_post_threei_size && ret == 0; i++)
71*4882a593Smuzhiyun     {
72*4882a593Smuzhiyun 	struct cpu_post_threei_s *test = cpu_post_threei_table + i;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	for (reg = 0; reg < 32 && ret == 0; reg++)
75*4882a593Smuzhiyun 	{
76*4882a593Smuzhiyun 	    unsigned int reg0 = (reg + 0) % 32;
77*4882a593Smuzhiyun 	    unsigned int reg1 = (reg + 1) % 32;
78*4882a593Smuzhiyun 	    unsigned int stk = reg < 16 ? 31 : 15;
79*4882a593Smuzhiyun 	    unsigned long code[] =
80*4882a593Smuzhiyun 	    {
81*4882a593Smuzhiyun 		ASM_STW(stk, 1, -4),
82*4882a593Smuzhiyun 		ASM_ADDI(stk, 1, -16),
83*4882a593Smuzhiyun 		ASM_STW(3, stk, 8),
84*4882a593Smuzhiyun 		ASM_STW(reg0, stk, 4),
85*4882a593Smuzhiyun 		ASM_STW(reg1, stk, 0),
86*4882a593Smuzhiyun 		ASM_LWZ(reg0, stk, 8),
87*4882a593Smuzhiyun 		ASM_11IX(test->cmd, reg1, reg0, test->op2),
88*4882a593Smuzhiyun 		ASM_STW(reg1, stk, 8),
89*4882a593Smuzhiyun 		ASM_LWZ(reg1, stk, 0),
90*4882a593Smuzhiyun 		ASM_LWZ(reg0, stk, 4),
91*4882a593Smuzhiyun 		ASM_LWZ(3, stk, 8),
92*4882a593Smuzhiyun 		ASM_ADDI(1, stk, 16),
93*4882a593Smuzhiyun 		ASM_LWZ(stk, 1, -4),
94*4882a593Smuzhiyun 		ASM_BLR,
95*4882a593Smuzhiyun 	    };
96*4882a593Smuzhiyun 	    ulong res;
97*4882a593Smuzhiyun 	    ulong cr;
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	    cr = 0;
100*4882a593Smuzhiyun 	    cpu_post_exec_21 (code, & cr, & res, test->op1);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	    ret = res == test->res && cr == 0 ? 0 : -1;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	    if (ret != 0)
105*4882a593Smuzhiyun 	    {
106*4882a593Smuzhiyun 		post_log ("Error at threei test %d !\n", i);
107*4882a593Smuzhiyun 	    }
108*4882a593Smuzhiyun 	}
109*4882a593Smuzhiyun     }
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun     if (flag)
112*4882a593Smuzhiyun 	enable_interrupts();
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun     return ret;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun #endif
118