1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2002
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /*
11*4882a593Smuzhiyun * CPU test
12*4882a593Smuzhiyun * Logic instructions: andi., andis.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * The test contains a pre-built table of instructions, operands and
15*4882a593Smuzhiyun * expected results. For each table entry, the test will cyclically use
16*4882a593Smuzhiyun * different sets of operand registers and result registers.
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <post.h>
20*4882a593Smuzhiyun #include "cpu_asm.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #if CONFIG_POST & CONFIG_SYS_POST_CPU
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
25*4882a593Smuzhiyun extern ulong cpu_post_makecr (long v);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static struct cpu_post_andi_s
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun ulong cmd;
30*4882a593Smuzhiyun ulong op1;
31*4882a593Smuzhiyun ushort op2;
32*4882a593Smuzhiyun ulong res;
33*4882a593Smuzhiyun } cpu_post_andi_table[] =
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun OP_ANDI_,
37*4882a593Smuzhiyun 0x80008000,
38*4882a593Smuzhiyun 0xffff,
39*4882a593Smuzhiyun 0x00008000
40*4882a593Smuzhiyun },
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun OP_ANDIS_,
43*4882a593Smuzhiyun 0x80008000,
44*4882a593Smuzhiyun 0xffff,
45*4882a593Smuzhiyun 0x80000000
46*4882a593Smuzhiyun },
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun static unsigned int cpu_post_andi_size = ARRAY_SIZE(cpu_post_andi_table);
49*4882a593Smuzhiyun
cpu_post_test_andi(void)50*4882a593Smuzhiyun int cpu_post_test_andi (void)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun int ret = 0;
53*4882a593Smuzhiyun unsigned int i, reg;
54*4882a593Smuzhiyun int flag = disable_interrupts();
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun for (i = 0; i < cpu_post_andi_size && ret == 0; i++)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun struct cpu_post_andi_s *test = cpu_post_andi_table + i;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun for (reg = 0; reg < 32 && ret == 0; reg++)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun unsigned int reg0 = (reg + 0) % 32;
63*4882a593Smuzhiyun unsigned int reg1 = (reg + 1) % 32;
64*4882a593Smuzhiyun unsigned int stk = reg < 16 ? 31 : 15;
65*4882a593Smuzhiyun unsigned long codecr[] =
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun ASM_STW(stk, 1, -4),
68*4882a593Smuzhiyun ASM_ADDI(stk, 1, -16),
69*4882a593Smuzhiyun ASM_STW(3, stk, 8),
70*4882a593Smuzhiyun ASM_STW(reg0, stk, 4),
71*4882a593Smuzhiyun ASM_STW(reg1, stk, 0),
72*4882a593Smuzhiyun ASM_LWZ(reg0, stk, 8),
73*4882a593Smuzhiyun ASM_11IX(test->cmd, reg1, reg0, test->op2),
74*4882a593Smuzhiyun ASM_STW(reg1, stk, 8),
75*4882a593Smuzhiyun ASM_LWZ(reg1, stk, 0),
76*4882a593Smuzhiyun ASM_LWZ(reg0, stk, 4),
77*4882a593Smuzhiyun ASM_LWZ(3, stk, 8),
78*4882a593Smuzhiyun ASM_ADDI(1, stk, 16),
79*4882a593Smuzhiyun ASM_LWZ(stk, 1, -4),
80*4882a593Smuzhiyun ASM_BLR,
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun ulong res;
83*4882a593Smuzhiyun ulong cr;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun cpu_post_exec_21 (codecr, & cr, & res, test->op1);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun ret = res == test->res &&
88*4882a593Smuzhiyun (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun if (ret != 0)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun post_log ("Error at andi test %d !\n", i);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (flag)
98*4882a593Smuzhiyun enable_interrupts();
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return ret;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #endif
104