1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2012-2013, Xilinx, Michal Simek 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2012 5*4882a593Smuzhiyun * Joe Hershberger <joe.hershberger@ni.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _ZYNQPL_H_ 11*4882a593Smuzhiyun #define _ZYNQPL_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <xilinx.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #if defined(CONFIG_FPGA_ZYNQPL) 16*4882a593Smuzhiyun extern struct xilinx_fpga_op zynq_op; 17*4882a593Smuzhiyun # define FPGA_ZYNQPL_OPS &zynq_op 18*4882a593Smuzhiyun #else 19*4882a593Smuzhiyun # define FPGA_ZYNQPL_OPS NULL 20*4882a593Smuzhiyun #endif 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define XILINX_ZYNQ_7007S 0x3 23*4882a593Smuzhiyun #define XILINX_ZYNQ_7010 0x2 24*4882a593Smuzhiyun #define XILINX_ZYNQ_7012S 0x1c 25*4882a593Smuzhiyun #define XILINX_ZYNQ_7014S 0x8 26*4882a593Smuzhiyun #define XILINX_ZYNQ_7015 0x1b 27*4882a593Smuzhiyun #define XILINX_ZYNQ_7020 0x7 28*4882a593Smuzhiyun #define XILINX_ZYNQ_7030 0xc 29*4882a593Smuzhiyun #define XILINX_ZYNQ_7035 0x12 30*4882a593Smuzhiyun #define XILINX_ZYNQ_7045 0x11 31*4882a593Smuzhiyun #define XILINX_ZYNQ_7100 0x16 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Device Image Sizes */ 34*4882a593Smuzhiyun #define XILINX_XC7Z007S_SIZE 16669920/8 35*4882a593Smuzhiyun #define XILINX_XC7Z010_SIZE 16669920/8 36*4882a593Smuzhiyun #define XILINX_XC7Z012S_SIZE 28085344/8 37*4882a593Smuzhiyun #define XILINX_XC7Z014S_SIZE 32364512/8 38*4882a593Smuzhiyun #define XILINX_XC7Z015_SIZE 28085344/8 39*4882a593Smuzhiyun #define XILINX_XC7Z020_SIZE 32364512/8 40*4882a593Smuzhiyun #define XILINX_XC7Z030_SIZE 47839328/8 41*4882a593Smuzhiyun #define XILINX_XC7Z035_SIZE 106571232/8 42*4882a593Smuzhiyun #define XILINX_XC7Z045_SIZE 106571232/8 43*4882a593Smuzhiyun #define XILINX_XC7Z100_SIZE 139330784/8 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Descriptor Macros */ 46*4882a593Smuzhiyun #define XILINX_XC7Z007S_DESC(cookie) \ 47*4882a593Smuzhiyun { xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 48*4882a593Smuzhiyun "7z007s" } 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define XILINX_XC7Z010_DESC(cookie) \ 51*4882a593Smuzhiyun { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 52*4882a593Smuzhiyun "7z010" } 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define XILINX_XC7Z012S_DESC(cookie) \ 55*4882a593Smuzhiyun { xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 56*4882a593Smuzhiyun "7z012s" } 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define XILINX_XC7Z014S_DESC(cookie) \ 59*4882a593Smuzhiyun { xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 60*4882a593Smuzhiyun "7z014s" } 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define XILINX_XC7Z015_DESC(cookie) \ 63*4882a593Smuzhiyun { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 64*4882a593Smuzhiyun "7z015" } 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define XILINX_XC7Z020_DESC(cookie) \ 67*4882a593Smuzhiyun { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 68*4882a593Smuzhiyun "7z020" } 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define XILINX_XC7Z030_DESC(cookie) \ 71*4882a593Smuzhiyun { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 72*4882a593Smuzhiyun "7z030" } 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define XILINX_XC7Z035_DESC(cookie) \ 75*4882a593Smuzhiyun { xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 76*4882a593Smuzhiyun "7z035" } 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define XILINX_XC7Z045_DESC(cookie) \ 79*4882a593Smuzhiyun { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 80*4882a593Smuzhiyun "7z045" } 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define XILINX_XC7Z100_DESC(cookie) \ 83*4882a593Smuzhiyun { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 84*4882a593Smuzhiyun "7z100" } 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif /* _ZYNQPL_H_ */ 87