1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2015 Xilinx, Inc, 3*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ZYNQMPPL_H_ 9*4882a593Smuzhiyun #define _ZYNQMPPL_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <xilinx.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018 14*4882a593Smuzhiyun #define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016 15*4882a593Smuzhiyun #define ZYNQMP_FPGA_OP_INIT (1 << 0) 16*4882a593Smuzhiyun #define ZYNQMP_FPGA_OP_LOAD (1 << 1) 17*4882a593Smuzhiyun #define ZYNQMP_FPGA_OP_DONE (1 << 2) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 20*4882a593Smuzhiyun #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \ 21*4882a593Smuzhiyun ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) 22*4882a593Smuzhiyun #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 23*4882a593Smuzhiyun #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun extern struct xilinx_fpga_op zynqmp_op; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define XILINX_ZYNQMP_DESC \ 28*4882a593Smuzhiyun { xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op } 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #endif /* _ZYNQMPPL_H_ */ 31