1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2002 3*4882a593Smuzhiyun * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <fpga.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _XILINX_H_ 11*4882a593Smuzhiyun #define _XILINX_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Xilinx types 14*4882a593Smuzhiyun *********************************************************************/ 15*4882a593Smuzhiyun typedef enum { /* typedef xilinx_iface */ 16*4882a593Smuzhiyun min_xilinx_iface_type, /* low range check value */ 17*4882a593Smuzhiyun slave_serial, /* serial data and external clock */ 18*4882a593Smuzhiyun master_serial, /* serial data w/ internal clock (not used) */ 19*4882a593Smuzhiyun slave_parallel, /* parallel data w/ external latch */ 20*4882a593Smuzhiyun jtag_mode, /* jtag/tap serial (not used ) */ 21*4882a593Smuzhiyun master_selectmap, /* master SelectMap (virtex2) */ 22*4882a593Smuzhiyun slave_selectmap, /* slave SelectMap (virtex2) */ 23*4882a593Smuzhiyun devcfg, /* devcfg interface (zynq) */ 24*4882a593Smuzhiyun csu_dma, /* csu_dma interface (zynqmp) */ 25*4882a593Smuzhiyun max_xilinx_iface_type /* insert all new types before this */ 26*4882a593Smuzhiyun } xilinx_iface; /* end, typedef xilinx_iface */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun typedef enum { /* typedef xilinx_family */ 29*4882a593Smuzhiyun min_xilinx_type, /* low range check value */ 30*4882a593Smuzhiyun xilinx_spartan2, /* Spartan-II Family */ 31*4882a593Smuzhiyun xilinx_virtexE, /* Virtex-E Family */ 32*4882a593Smuzhiyun xilinx_virtex2, /* Virtex2 Family */ 33*4882a593Smuzhiyun xilinx_spartan3, /* Spartan-III Family */ 34*4882a593Smuzhiyun xilinx_zynq, /* Zynq Family */ 35*4882a593Smuzhiyun xilinx_zynqmp, /* ZynqMP Family */ 36*4882a593Smuzhiyun max_xilinx_type /* insert all new types before this */ 37*4882a593Smuzhiyun } xilinx_family; /* end, typedef xilinx_family */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun typedef struct { /* typedef xilinx_desc */ 40*4882a593Smuzhiyun xilinx_family family; /* part type */ 41*4882a593Smuzhiyun xilinx_iface iface; /* interface type */ 42*4882a593Smuzhiyun size_t size; /* bytes of data part can accept */ 43*4882a593Smuzhiyun void *iface_fns; /* interface function table */ 44*4882a593Smuzhiyun int cookie; /* implementation specific cookie */ 45*4882a593Smuzhiyun struct xilinx_fpga_op *operations; /* operations */ 46*4882a593Smuzhiyun char *name; /* device name in bitstream */ 47*4882a593Smuzhiyun } xilinx_desc; /* end, typedef xilinx_desc */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun struct xilinx_fpga_op { 50*4882a593Smuzhiyun int (*load)(xilinx_desc *, const void *, size_t, bitstream_type); 51*4882a593Smuzhiyun int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *); 52*4882a593Smuzhiyun int (*dump)(xilinx_desc *, const void *, size_t); 53*4882a593Smuzhiyun int (*info)(xilinx_desc *); 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Generic Xilinx Functions 57*4882a593Smuzhiyun *********************************************************************/ 58*4882a593Smuzhiyun int xilinx_load(xilinx_desc *desc, const void *image, size_t size, 59*4882a593Smuzhiyun bitstream_type bstype); 60*4882a593Smuzhiyun int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize); 61*4882a593Smuzhiyun int xilinx_info(xilinx_desc *desc); 62*4882a593Smuzhiyun int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, 63*4882a593Smuzhiyun fpga_fs_info *fpga_fsinfo); 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Board specific implementation specific function types 66*4882a593Smuzhiyun *********************************************************************/ 67*4882a593Smuzhiyun typedef int (*xilinx_pgm_fn)(int assert_pgm, int flush, int cookie); 68*4882a593Smuzhiyun typedef int (*xilinx_init_fn)(int cookie); 69*4882a593Smuzhiyun typedef int (*xilinx_err_fn)(int cookie); 70*4882a593Smuzhiyun typedef int (*xilinx_done_fn)(int cookie); 71*4882a593Smuzhiyun typedef int (*xilinx_clk_fn)(int assert_clk, int flush, int cookie); 72*4882a593Smuzhiyun typedef int (*xilinx_cs_fn)(int assert_cs, int flush, int cookie); 73*4882a593Smuzhiyun typedef int (*xilinx_wr_fn)(int assert_write, int flush, int cookie); 74*4882a593Smuzhiyun typedef int (*xilinx_rdata_fn)(unsigned char *data, int cookie); 75*4882a593Smuzhiyun typedef int (*xilinx_wdata_fn)(unsigned char data, int flush, int cookie); 76*4882a593Smuzhiyun typedef int (*xilinx_busy_fn)(int cookie); 77*4882a593Smuzhiyun typedef int (*xilinx_abort_fn)(int cookie); 78*4882a593Smuzhiyun typedef int (*xilinx_pre_fn)(int cookie); 79*4882a593Smuzhiyun typedef int (*xilinx_post_fn)(int cookie); 80*4882a593Smuzhiyun typedef int (*xilinx_bwr_fn)(void *buf, size_t len, int flush, int cookie); 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #endif /* _XILINX_H_ */ 83