1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _WINBOND_W83627_H_ 8*4882a593Smuzhiyun #define _WINBOND_W83627_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* I/O address of Winbond Super IO chip */ 11*4882a593Smuzhiyun #define WINBOND_IO_PORT 0x2e 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Logical device number */ 14*4882a593Smuzhiyun #define W83627DHG_FDC 0 /* Floppy */ 15*4882a593Smuzhiyun #define W83627DHG_PP 1 /* Parallel port */ 16*4882a593Smuzhiyun #define W83627DHG_SP1 2 /* Com1 */ 17*4882a593Smuzhiyun #define W83627DHG_SP2 3 /* Com2 */ 18*4882a593Smuzhiyun #define W83627DHG_KBC 5 /* PS/2 keyboard & mouse */ 19*4882a593Smuzhiyun #define W83627DHG_SPI 6 /* Serial peripheral interface */ 20*4882a593Smuzhiyun #define W83627DHG_WDTO_PLED 8 /* WDTO#, PLED */ 21*4882a593Smuzhiyun #define W83627DHG_ACPI 10 /* ACPI */ 22*4882a593Smuzhiyun #define W83627DHG_HWM 11 /* Hardware monitor */ 23*4882a593Smuzhiyun #define W83627DHG_PECI_SST 12 /* PECI, SST */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /** 26*4882a593Smuzhiyun * Configure the base I/O port of the specified serial device and enable the 27*4882a593Smuzhiyun * serial device. 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * @dev: high 8 bits = super I/O port, low 8 bits = logical device number 30*4882a593Smuzhiyun * @iobase: processor I/O port address to assign to this serial device 31*4882a593Smuzhiyun * @irq: processor IRQ number to assign to this serial device 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun void winbond_enable_serial(uint dev, uint iobase, uint irq); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #endif /* _WINBOND_W83627_H_ */ 36