1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Wait for bit with timeout and ctrlc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __WAIT_BIT_H 10*4882a593Smuzhiyun #define __WAIT_BIT_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <common.h> 13*4882a593Smuzhiyun #include <console.h> 14*4882a593Smuzhiyun #include <watchdog.h> 15*4882a593Smuzhiyun #include <linux/errno.h> 16*4882a593Smuzhiyun #include <asm/io.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /** 19*4882a593Smuzhiyun * wait_for_bit_x() waits for bit set/cleared in register 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * Function polls register waiting for specific bit(s) change 22*4882a593Smuzhiyun * (either 0->1 or 1->0). It can fail under two conditions: 23*4882a593Smuzhiyun * - Timeout 24*4882a593Smuzhiyun * - User interaction (CTRL-C) 25*4882a593Smuzhiyun * Function succeeds only if all bits of masked register are set/cleared 26*4882a593Smuzhiyun * (depending on set option). 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * @param reg Register that will be read (using read_x()) 29*4882a593Smuzhiyun * @param mask Bit(s) of register that must be active 30*4882a593Smuzhiyun * @param set Selects wait condition (bit set or clear) 31*4882a593Smuzhiyun * @param timeout_ms Timeout (in milliseconds) 32*4882a593Smuzhiyun * @param breakable Enables CTRL-C interruption 33*4882a593Smuzhiyun * @return 0 on success, -ETIMEDOUT or -EINTR on failure 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define BUILD_WAIT_FOR_BIT(sfx, type, read) \ 37*4882a593Smuzhiyun \ 38*4882a593Smuzhiyun static inline int wait_for_bit_##sfx(const void *reg, \ 39*4882a593Smuzhiyun const type mask, \ 40*4882a593Smuzhiyun const bool set, \ 41*4882a593Smuzhiyun const unsigned int timeout_ms, \ 42*4882a593Smuzhiyun const bool breakable) \ 43*4882a593Smuzhiyun { \ 44*4882a593Smuzhiyun type val; \ 45*4882a593Smuzhiyun unsigned long start = get_timer(0); \ 46*4882a593Smuzhiyun \ 47*4882a593Smuzhiyun while (1) { \ 48*4882a593Smuzhiyun val = read(reg); \ 49*4882a593Smuzhiyun \ 50*4882a593Smuzhiyun if (!set) \ 51*4882a593Smuzhiyun val = ~val; \ 52*4882a593Smuzhiyun \ 53*4882a593Smuzhiyun if ((val & mask) == mask) \ 54*4882a593Smuzhiyun return 0; \ 55*4882a593Smuzhiyun \ 56*4882a593Smuzhiyun if (get_timer(start) > timeout_ms) \ 57*4882a593Smuzhiyun break; \ 58*4882a593Smuzhiyun \ 59*4882a593Smuzhiyun if (breakable && ctrlc()) { \ 60*4882a593Smuzhiyun puts("Abort\n"); \ 61*4882a593Smuzhiyun return -EINTR; \ 62*4882a593Smuzhiyun } \ 63*4882a593Smuzhiyun \ 64*4882a593Smuzhiyun udelay(1); \ 65*4882a593Smuzhiyun WATCHDOG_RESET(); \ 66*4882a593Smuzhiyun } \ 67*4882a593Smuzhiyun \ 68*4882a593Smuzhiyun debug("%s: Timeout (reg=%p mask=%x wait_set=%i)\n", __func__, \ 69*4882a593Smuzhiyun reg, mask, set); \ 70*4882a593Smuzhiyun \ 71*4882a593Smuzhiyun return -ETIMEDOUT; \ 72*4882a593Smuzhiyun } 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun BUILD_WAIT_FOR_BIT(8, u8, readb) 75*4882a593Smuzhiyun BUILD_WAIT_FOR_BIT(le16, u16, readw) 76*4882a593Smuzhiyun #ifdef readw_be 77*4882a593Smuzhiyun BUILD_WAIT_FOR_BIT(be16, u16, readw_be) 78*4882a593Smuzhiyun #endif 79*4882a593Smuzhiyun BUILD_WAIT_FOR_BIT(le32, u32, readl) 80*4882a593Smuzhiyun #ifdef readl_be 81*4882a593Smuzhiyun BUILD_WAIT_FOR_BIT(be32, u32, readl_be) 82*4882a593Smuzhiyun #endif 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #endif 85