1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2002 3*4882a593Smuzhiyun * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4*4882a593Smuzhiyun * Keith Outwater, keith_outwater@mvis.com 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _VIRTEX2_H_ 10*4882a593Smuzhiyun #define _VIRTEX2_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <xilinx.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Slave SelectMap Implementation function table. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun typedef struct { 18*4882a593Smuzhiyun xilinx_pre_fn pre; 19*4882a593Smuzhiyun xilinx_pgm_fn pgm; 20*4882a593Smuzhiyun xilinx_init_fn init; 21*4882a593Smuzhiyun xilinx_err_fn err; 22*4882a593Smuzhiyun xilinx_done_fn done; 23*4882a593Smuzhiyun xilinx_clk_fn clk; 24*4882a593Smuzhiyun xilinx_cs_fn cs; 25*4882a593Smuzhiyun xilinx_wr_fn wr; 26*4882a593Smuzhiyun xilinx_rdata_fn rdata; 27*4882a593Smuzhiyun xilinx_wdata_fn wdata; 28*4882a593Smuzhiyun xilinx_busy_fn busy; 29*4882a593Smuzhiyun xilinx_abort_fn abort; 30*4882a593Smuzhiyun xilinx_post_fn post; 31*4882a593Smuzhiyun } xilinx_virtex2_slave_selectmap_fns; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Slave Serial Implementation function table */ 34*4882a593Smuzhiyun typedef struct { 35*4882a593Smuzhiyun xilinx_pgm_fn pgm; 36*4882a593Smuzhiyun xilinx_clk_fn clk; 37*4882a593Smuzhiyun xilinx_rdata_fn rdata; 38*4882a593Smuzhiyun xilinx_wdata_fn wdata; 39*4882a593Smuzhiyun } xilinx_virtex2_slave_serial_fns; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #if defined(CONFIG_FPGA_VIRTEX2) 42*4882a593Smuzhiyun extern struct xilinx_fpga_op virtex2_op; 43*4882a593Smuzhiyun # define FPGA_VIRTEX2_OPS &virtex2_op 44*4882a593Smuzhiyun #else 45*4882a593Smuzhiyun # define FPGA_VIRTEX2_OPS NULL 46*4882a593Smuzhiyun #endif 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Device Image Sizes (in bytes) 49*4882a593Smuzhiyun *********************************************************************/ 50*4882a593Smuzhiyun #define XILINX_XC2V40_SIZE (338208 / 8) 51*4882a593Smuzhiyun #define XILINX_XC2V80_SIZE (597408 / 8) 52*4882a593Smuzhiyun #define XILINX_XC2V250_SIZE (1591584 / 8) 53*4882a593Smuzhiyun #define XILINX_XC2V500_SIZE (2557857 / 8) 54*4882a593Smuzhiyun #define XILINX_XC2V1000_SIZE (3749408 / 8) 55*4882a593Smuzhiyun #define XILINX_XC2V1500_SIZE (5166240 / 8) 56*4882a593Smuzhiyun #define XILINX_XC2V2000_SIZE (6808352 / 8) 57*4882a593Smuzhiyun #define XILINX_XC2V3000_SIZE (9589408 / 8) 58*4882a593Smuzhiyun #define XILINX_XC2V4000_SIZE (14220192 / 8) 59*4882a593Smuzhiyun #define XILINX_XC2V6000_SIZE (19752096 / 8) 60*4882a593Smuzhiyun #define XILINX_XC2V8000_SIZE (26185120 / 8) 61*4882a593Smuzhiyun #define XILINX_XC2V10000_SIZE (33519264 / 8) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Descriptor Macros 64*4882a593Smuzhiyun *********************************************************************/ 65*4882a593Smuzhiyun #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \ 66*4882a593Smuzhiyun { xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \ 67*4882a593Smuzhiyun FPGA_VIRTEX2_OPS } 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \ 70*4882a593Smuzhiyun { xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \ 71*4882a593Smuzhiyun FPGA_VIRTEX2_OPS } 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \ 74*4882a593Smuzhiyun { xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \ 75*4882a593Smuzhiyun FPGA_VIRTEX2_OPS } 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \ 78*4882a593Smuzhiyun { xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \ 79*4882a593Smuzhiyun FPGA_VIRTEX2_OPS } 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \ 82*4882a593Smuzhiyun { xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \ 83*4882a593Smuzhiyun FPGA_VIRTEX2_OPS } 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \ 86*4882a593Smuzhiyun { xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \ 87*4882a593Smuzhiyun FPGA_VIRTEX2_OPS } 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \ 90*4882a593Smuzhiyun { xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \ 91*4882a593Smuzhiyun FPGA_VIRTEX2_OPS } 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \ 94*4882a593Smuzhiyun { xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \ 95*4882a593Smuzhiyun FPGA_VIRTEX2_OPS } 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \ 98*4882a593Smuzhiyun { xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \ 99*4882a593Smuzhiyun FPGA_VIRTEX2_OPS } 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \ 102*4882a593Smuzhiyun { xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \ 103*4882a593Smuzhiyun FPGA_VIRTEX2_OPS } 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \ 106*4882a593Smuzhiyun { xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \ 107*4882a593Smuzhiyun FPGA_VIRTEX2_OPS } 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \ 110*4882a593Smuzhiyun { xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \ 111*4882a593Smuzhiyun FPGA_VIRTEX2_OPS } 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #endif /* _VIRTEX2_H_ */ 114