1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Faraday USB 2.0 EHCI Controller 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2010 Faraday Technology 5*4882a593Smuzhiyun * Dante Su <dantesu@faraday-tech.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _FUSBH200_H 11*4882a593Smuzhiyun #define _FUSBH200_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct fusbh200_regs { 14*4882a593Smuzhiyun struct { 15*4882a593Smuzhiyun uint32_t data[4]; 16*4882a593Smuzhiyun } hccr; /* 0x00 - 0x0f: hccr */ 17*4882a593Smuzhiyun struct { 18*4882a593Smuzhiyun uint32_t data[9]; 19*4882a593Smuzhiyun } hcor; /* 0x10 - 0x33: hcor */ 20*4882a593Smuzhiyun uint32_t easstr;/* 0x34: EOF&Async. Sched. Sleep Timer Register */ 21*4882a593Smuzhiyun uint32_t rsvd[2]; 22*4882a593Smuzhiyun uint32_t bmcsr; /* 0x40: Bus Monitor Control Status Register */ 23*4882a593Smuzhiyun uint32_t bmisr; /* 0x44: Bus Monitor Interrupt Status Register */ 24*4882a593Smuzhiyun uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */ 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* EOF & Async. Schedule Sleep Timer Register */ 28*4882a593Smuzhiyun #define EASSTR_RUNNING (1 << 6) /* Put transceiver in running/resume mode */ 29*4882a593Smuzhiyun #define EASSTR_SUSPEND (0 << 6) /* Put transceiver in suspend mode */ 30*4882a593Smuzhiyun #define EASSTR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */ 31*4882a593Smuzhiyun #define EASSTR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */ 32*4882a593Smuzhiyun #define EASSTR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Bus Monitor Control Status Register */ 35*4882a593Smuzhiyun #define BMCSR_SPD_HIGH (2 << 9) /* Speed of the attached device */ 36*4882a593Smuzhiyun #define BMCSR_SPD_LOW (1 << 9) 37*4882a593Smuzhiyun #define BMCSR_SPD_FULL (0 << 9) 38*4882a593Smuzhiyun #define BMCSR_SPD_MASK (3 << 9) 39*4882a593Smuzhiyun #define BMCSR_SPD_SHIFT 9 40*4882a593Smuzhiyun #define BMCSR_SPD(x) ((x >> 9) & 0x03) 41*4882a593Smuzhiyun #define BMCSR_VBUS (1 << 8) /* VBUS Valid */ 42*4882a593Smuzhiyun #define BMCSR_VBUS_OFF (1 << 4) /* VBUS Off */ 43*4882a593Smuzhiyun #define BMCSR_VBUS_ON (0 << 4) /* VBUS On */ 44*4882a593Smuzhiyun #define BMCSR_IRQLH (1 << 3) /* IRQ triggered at level-high */ 45*4882a593Smuzhiyun #define BMCSR_IRQLL (0 << 3) /* IRQ triggered at level-low */ 46*4882a593Smuzhiyun #define BMCSR_HALFSPD (1 << 2) /* Half speed mode for FPGA test */ 47*4882a593Smuzhiyun #define BMCSR_HFT_LONG (1 << 1) /* HDISCON noise filter = 270 us*/ 48*4882a593Smuzhiyun #define BMCSR_HFT (0 << 1) /* HDISCON noise filter = 135 us*/ 49*4882a593Smuzhiyun #define BMCSR_VFT_LONG (1 << 1) /* VBUS noise filter = 472 us*/ 50*4882a593Smuzhiyun #define BMCSR_VFT (0 << 1) /* VBUS noise filter = 135 us*/ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Bus Monitor Interrupt Status Register */ 53*4882a593Smuzhiyun /* Bus Monitor Interrupt Enable Register */ 54*4882a593Smuzhiyun #define BMISR_DMAERR (1 << 4) /* DMA error */ 55*4882a593Smuzhiyun #define BMISR_DMA (1 << 3) /* DMA complete */ 56*4882a593Smuzhiyun #define BMISR_DEVRM (1 << 2) /* device removed */ 57*4882a593Smuzhiyun #define BMISR_OVD (1 << 1) /* over-current detected */ 58*4882a593Smuzhiyun #define BMISR_VBUSERR (1 << 0) /* VBUS error */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif 61