1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 3*4882a593Smuzhiyun * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DW_UDC_H 9*4882a593Smuzhiyun #define __DW_UDC_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Defines for USBD 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * The udc_ahb controller has three AHB slaves: 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * 1. THe UDC registers 17*4882a593Smuzhiyun * 2. The plug detect 18*4882a593Smuzhiyun * 3. The RX/TX FIFO 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define MAX_ENDPOINTS 16 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct udc_endp_regs { 24*4882a593Smuzhiyun u32 endp_cntl; 25*4882a593Smuzhiyun u32 endp_status; 26*4882a593Smuzhiyun u32 endp_bsorfn; 27*4882a593Smuzhiyun u32 endp_maxpacksize; 28*4882a593Smuzhiyun u32 reserved_1; 29*4882a593Smuzhiyun u32 endp_desc_point; 30*4882a593Smuzhiyun u32 reserved_2; 31*4882a593Smuzhiyun u32 write_done; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Endpoint Control Register definitions */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define ENDP_CNTL_STALL 0x00000001 37*4882a593Smuzhiyun #define ENDP_CNTL_FLUSH 0x00000002 38*4882a593Smuzhiyun #define ENDP_CNTL_SNOOP 0x00000004 39*4882a593Smuzhiyun #define ENDP_CNTL_POLL 0x00000008 40*4882a593Smuzhiyun #define ENDP_CNTL_CONTROL 0x00000000 41*4882a593Smuzhiyun #define ENDP_CNTL_ISO 0x00000010 42*4882a593Smuzhiyun #define ENDP_CNTL_BULK 0x00000020 43*4882a593Smuzhiyun #define ENDP_CNTL_INT 0x00000030 44*4882a593Smuzhiyun #define ENDP_CNTL_NAK 0x00000040 45*4882a593Smuzhiyun #define ENDP_CNTL_SNAK 0x00000080 46*4882a593Smuzhiyun #define ENDP_CNTL_CNAK 0x00000100 47*4882a593Smuzhiyun #define ENDP_CNTL_RRDY 0x00000200 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Endpoint Satus Register definitions */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define ENDP_STATUS_PIDMSK 0x0000000f 52*4882a593Smuzhiyun #define ENDP_STATUS_OUTMSK 0x00000030 53*4882a593Smuzhiyun #define ENDP_STATUS_OUT_NONE 0x00000000 54*4882a593Smuzhiyun #define ENDP_STATUS_OUT_DATA 0x00000010 55*4882a593Smuzhiyun #define ENDP_STATUS_OUT_SETUP 0x00000020 56*4882a593Smuzhiyun #define ENDP_STATUS_IN 0x00000040 57*4882a593Smuzhiyun #define ENDP_STATUS_BUFFNAV 0x00000080 58*4882a593Smuzhiyun #define ENDP_STATUS_FATERR 0x00000100 59*4882a593Smuzhiyun #define ENDP_STATUS_HOSTBUSERR 0x00000200 60*4882a593Smuzhiyun #define ENDP_STATUS_TDC 0x00000400 61*4882a593Smuzhiyun #define ENDP_STATUS_RXPKTMSK 0x003ff800 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun struct udc_regs { 64*4882a593Smuzhiyun struct udc_endp_regs in_regs[MAX_ENDPOINTS]; 65*4882a593Smuzhiyun struct udc_endp_regs out_regs[MAX_ENDPOINTS]; 66*4882a593Smuzhiyun u32 dev_conf; 67*4882a593Smuzhiyun u32 dev_cntl; 68*4882a593Smuzhiyun u32 dev_stat; 69*4882a593Smuzhiyun u32 dev_int; 70*4882a593Smuzhiyun u32 dev_int_mask; 71*4882a593Smuzhiyun u32 endp_int; 72*4882a593Smuzhiyun u32 endp_int_mask; 73*4882a593Smuzhiyun u32 reserved_3[0x39]; 74*4882a593Smuzhiyun u32 reserved_4; /* offset 0x500 */ 75*4882a593Smuzhiyun u32 udc_endp_reg[MAX_ENDPOINTS]; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Device Configuration Register definitions */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define DEV_CONF_HS_SPEED 0x00000000 81*4882a593Smuzhiyun #define DEV_CONF_LS_SPEED 0x00000002 82*4882a593Smuzhiyun #define DEV_CONF_FS_SPEED 0x00000003 83*4882a593Smuzhiyun #define DEV_CONF_REMWAKEUP 0x00000004 84*4882a593Smuzhiyun #define DEV_CONF_SELFPOW 0x00000008 85*4882a593Smuzhiyun #define DEV_CONF_SYNCFRAME 0x00000010 86*4882a593Smuzhiyun #define DEV_CONF_PHYINT_8 0x00000020 87*4882a593Smuzhiyun #define DEV_CONF_PHYINT_16 0x00000000 88*4882a593Smuzhiyun #define DEV_CONF_UTMI_BIDIR 0x00000040 89*4882a593Smuzhiyun #define DEV_CONF_STATUS_STALL 0x00000080 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* Device Control Register definitions */ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define DEV_CNTL_RESUME 0x00000001 94*4882a593Smuzhiyun #define DEV_CNTL_TFFLUSH 0x00000002 95*4882a593Smuzhiyun #define DEV_CNTL_RXDMAEN 0x00000004 96*4882a593Smuzhiyun #define DEV_CNTL_TXDMAEN 0x00000008 97*4882a593Smuzhiyun #define DEV_CNTL_DESCRUPD 0x00000010 98*4882a593Smuzhiyun #define DEV_CNTL_BIGEND 0x00000020 99*4882a593Smuzhiyun #define DEV_CNTL_BUFFILL 0x00000040 100*4882a593Smuzhiyun #define DEV_CNTL_TSHLDEN 0x00000080 101*4882a593Smuzhiyun #define DEV_CNTL_BURSTEN 0x00000100 102*4882a593Smuzhiyun #define DEV_CNTL_DMAMODE 0x00000200 103*4882a593Smuzhiyun #define DEV_CNTL_SOFTDISCONNECT 0x00000400 104*4882a593Smuzhiyun #define DEV_CNTL_SCALEDOWN 0x00000800 105*4882a593Smuzhiyun #define DEV_CNTL_BURSTLENU 0x00010000 106*4882a593Smuzhiyun #define DEV_CNTL_BURSTLENMSK 0x00ff0000 107*4882a593Smuzhiyun #define DEV_CNTL_TSHLDLENU 0x01000000 108*4882a593Smuzhiyun #define DEV_CNTL_TSHLDLENMSK 0xff000000 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* Device Status Register definitions */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define DEV_STAT_CFG 0x0000000f 113*4882a593Smuzhiyun #define DEV_STAT_INTF 0x000000f0 114*4882a593Smuzhiyun #define DEV_STAT_ALT 0x00000f00 115*4882a593Smuzhiyun #define DEV_STAT_SUSP 0x00001000 116*4882a593Smuzhiyun #define DEV_STAT_ENUM 0x00006000 117*4882a593Smuzhiyun #define DEV_STAT_ENUM_SPEED_HS 0x00000000 118*4882a593Smuzhiyun #define DEV_STAT_ENUM_SPEED_FS 0x00002000 119*4882a593Smuzhiyun #define DEV_STAT_ENUM_SPEED_LS 0x00004000 120*4882a593Smuzhiyun #define DEV_STAT_RXFIFO_EMPTY 0x00008000 121*4882a593Smuzhiyun #define DEV_STAT_PHY_ERR 0x00010000 122*4882a593Smuzhiyun #define DEV_STAT_TS 0xf0000000 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* Device Interrupt Register definitions */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define DEV_INT_MSK 0x0000007f 127*4882a593Smuzhiyun #define DEV_INT_SETCFG 0x00000001 128*4882a593Smuzhiyun #define DEV_INT_SETINTF 0x00000002 129*4882a593Smuzhiyun #define DEV_INT_INACTIVE 0x00000004 130*4882a593Smuzhiyun #define DEV_INT_USBRESET 0x00000008 131*4882a593Smuzhiyun #define DEV_INT_SUSPUSB 0x00000010 132*4882a593Smuzhiyun #define DEV_INT_SOF 0x00000020 133*4882a593Smuzhiyun #define DEV_INT_ENUM 0x00000040 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* Endpoint Interrupt Register definitions */ 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define ENDP0_INT_CTRLIN 0x00000001 138*4882a593Smuzhiyun #define ENDP1_INT_BULKIN 0x00000002 139*4882a593Smuzhiyun #define ENDP_INT_NONISOIN_MSK 0x0000AAAA 140*4882a593Smuzhiyun #define ENDP2_INT_BULKIN 0x00000004 141*4882a593Smuzhiyun #define ENDP0_INT_CTRLOUT 0x00010000 142*4882a593Smuzhiyun #define ENDP1_INT_BULKOUT 0x00020000 143*4882a593Smuzhiyun #define ENDP2_INT_BULKOUT 0x00040000 144*4882a593Smuzhiyun #define ENDP_INT_NONISOOUT_MSK 0x55540000 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* Endpoint Register definitions */ 147*4882a593Smuzhiyun #define ENDP_EPDIR_OUT 0x00000000 148*4882a593Smuzhiyun #define ENDP_EPDIR_IN 0x00000010 149*4882a593Smuzhiyun #define ENDP_EPTYPE_CNTL 0x0 150*4882a593Smuzhiyun #define ENDP_EPTYPE_ISO 0x1 151*4882a593Smuzhiyun #define ENDP_EPTYPE_BULK 0x2 152*4882a593Smuzhiyun #define ENDP_EPTYPE_INT 0x3 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* 155*4882a593Smuzhiyun * Defines for Plug Detect 156*4882a593Smuzhiyun */ 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun struct plug_regs { 159*4882a593Smuzhiyun u32 plug_state; 160*4882a593Smuzhiyun u32 plug_pending; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* Plug State Register definitions */ 164*4882a593Smuzhiyun #define PLUG_STATUS_EN 0x1 165*4882a593Smuzhiyun #define PLUG_STATUS_ATTACHED 0x2 166*4882a593Smuzhiyun #define PLUG_STATUS_PHY_RESET 0x4 167*4882a593Smuzhiyun #define PLUG_STATUS_PHY_MODE 0x8 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* 170*4882a593Smuzhiyun * Defines for UDC FIFO (Slave Mode) 171*4882a593Smuzhiyun */ 172*4882a593Smuzhiyun struct udcfifo_regs { 173*4882a593Smuzhiyun u32 *fifo_p; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* 177*4882a593Smuzhiyun * UDC endpoint definitions 178*4882a593Smuzhiyun */ 179*4882a593Smuzhiyun #define UDC_EP0 0 180*4882a593Smuzhiyun #define UDC_EP1 1 181*4882a593Smuzhiyun #define UDC_EP2 2 182*4882a593Smuzhiyun #define UDC_EP3 3 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #endif /* __DW_UDC_H */ 185