1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _universe_h 8*4882a593Smuzhiyun #define _universe_h 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun typedef struct _UNIVERSE UNIVERSE; 11*4882a593Smuzhiyun typedef struct _SLAVE_IMAGE SLAVE_IMAGE; 12*4882a593Smuzhiyun typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct _SLAVE_IMAGE { 15*4882a593Smuzhiyun unsigned int ctl; /* Control */ 16*4882a593Smuzhiyun unsigned int bs; /* Base */ 17*4882a593Smuzhiyun unsigned int bd; /* Bound */ 18*4882a593Smuzhiyun unsigned int to; /* Translation */ 19*4882a593Smuzhiyun unsigned int reserved; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct _UNIVERSE { 23*4882a593Smuzhiyun unsigned int pci_id; 24*4882a593Smuzhiyun unsigned int pci_csr; 25*4882a593Smuzhiyun unsigned int pci_class; 26*4882a593Smuzhiyun unsigned int pci_misc0; 27*4882a593Smuzhiyun unsigned int pci_bs; 28*4882a593Smuzhiyun unsigned int spare0[10]; 29*4882a593Smuzhiyun unsigned int pci_misc1; 30*4882a593Smuzhiyun unsigned int spare1[48]; 31*4882a593Smuzhiyun SLAVE_IMAGE lsi[4]; 32*4882a593Smuzhiyun unsigned int spare2[8]; 33*4882a593Smuzhiyun unsigned int scyc_ctl; 34*4882a593Smuzhiyun unsigned int scyc_addr; 35*4882a593Smuzhiyun unsigned int scyc_en; 36*4882a593Smuzhiyun unsigned int scyc_cmp; 37*4882a593Smuzhiyun unsigned int scyc_swp; 38*4882a593Smuzhiyun unsigned int lmisc; 39*4882a593Smuzhiyun unsigned int slsi; 40*4882a593Smuzhiyun unsigned int l_cmderr; 41*4882a593Smuzhiyun unsigned int laerr; 42*4882a593Smuzhiyun unsigned int spare3[27]; 43*4882a593Smuzhiyun unsigned int dctl; 44*4882a593Smuzhiyun unsigned int dtbc; 45*4882a593Smuzhiyun unsigned int dla; 46*4882a593Smuzhiyun unsigned int spare4[1]; 47*4882a593Smuzhiyun unsigned int dva; 48*4882a593Smuzhiyun unsigned int spare5[1]; 49*4882a593Smuzhiyun unsigned int dcpp; 50*4882a593Smuzhiyun unsigned int spare6[1]; 51*4882a593Smuzhiyun unsigned int dgcs; 52*4882a593Smuzhiyun unsigned int d_llue; 53*4882a593Smuzhiyun unsigned int spare7[54]; 54*4882a593Smuzhiyun unsigned int lint_en; 55*4882a593Smuzhiyun unsigned int lint_stat; 56*4882a593Smuzhiyun unsigned int lint_map0; 57*4882a593Smuzhiyun unsigned int lint_map1; 58*4882a593Smuzhiyun unsigned int vint_en; 59*4882a593Smuzhiyun unsigned int vint_stat; 60*4882a593Smuzhiyun unsigned int vint_map0; 61*4882a593Smuzhiyun unsigned int vint_map1; 62*4882a593Smuzhiyun unsigned int statid; 63*4882a593Smuzhiyun unsigned int vx_statid[7]; 64*4882a593Smuzhiyun unsigned int spare8[48]; 65*4882a593Smuzhiyun unsigned int mast_ctl; 66*4882a593Smuzhiyun unsigned int misc_ctl; 67*4882a593Smuzhiyun unsigned int misc_stat; 68*4882a593Smuzhiyun unsigned int user_am; 69*4882a593Smuzhiyun unsigned int spare9[700]; 70*4882a593Smuzhiyun SLAVE_IMAGE vsi[4]; 71*4882a593Smuzhiyun unsigned int spare10[8]; 72*4882a593Smuzhiyun unsigned int vrai_ctl; 73*4882a593Smuzhiyun unsigned int vrai_bs; 74*4882a593Smuzhiyun unsigned int spare11[2]; 75*4882a593Smuzhiyun unsigned int vcsr_ctl; 76*4882a593Smuzhiyun unsigned int vcsr_to; 77*4882a593Smuzhiyun unsigned int v_amerr; 78*4882a593Smuzhiyun unsigned int vaerr; 79*4882a593Smuzhiyun unsigned int spare12[25]; 80*4882a593Smuzhiyun unsigned int vcsr_clr; 81*4882a593Smuzhiyun unsigned int vcsr_set; 82*4882a593Smuzhiyun unsigned int vcsr_bs; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define IRQ_VOWN 0x0001 86*4882a593Smuzhiyun #define IRQ_VIRQ1 0x0002 87*4882a593Smuzhiyun #define IRQ_VIRQ2 0x0004 88*4882a593Smuzhiyun #define IRQ_VIRQ3 0x0008 89*4882a593Smuzhiyun #define IRQ_VIRQ4 0x0010 90*4882a593Smuzhiyun #define IRQ_VIRQ5 0x0020 91*4882a593Smuzhiyun #define IRQ_VIRQ6 0x0040 92*4882a593Smuzhiyun #define IRQ_VIRQ7 0x0080 93*4882a593Smuzhiyun #define IRQ_DMA 0x0100 94*4882a593Smuzhiyun #define IRQ_LERR 0x0200 95*4882a593Smuzhiyun #define IRQ_VERR 0x0400 96*4882a593Smuzhiyun #define IRQ_res 0x0800 97*4882a593Smuzhiyun #define IRQ_IACK 0x1000 98*4882a593Smuzhiyun #define IRQ_SWINT 0x2000 99*4882a593Smuzhiyun #define IRQ_SYSFAIL 0x4000 100*4882a593Smuzhiyun #define IRQ_ACFAIL 0x8000 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun struct _TDMA_CMD_PACKET { 103*4882a593Smuzhiyun unsigned int dctl; /* DMA Control */ 104*4882a593Smuzhiyun unsigned int dtbc; /* Transfer Byte Count */ 105*4882a593Smuzhiyun unsigned int dlv; /* PCI Address */ 106*4882a593Smuzhiyun unsigned int res1; /* Reserved */ 107*4882a593Smuzhiyun unsigned int dva; /* Vme Address */ 108*4882a593Smuzhiyun unsigned int res2; /* Reserved */ 109*4882a593Smuzhiyun unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */ 110*4882a593Smuzhiyun unsigned int res3; /* Reserved */ 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define VME_AM_A16 0x01 114*4882a593Smuzhiyun #define VME_AM_A24 0x02 115*4882a593Smuzhiyun #define VME_AM_A32 0x03 116*4882a593Smuzhiyun #define VME_AM_Axx 0x03 117*4882a593Smuzhiyun #define VME_AM_SUP 0x04 118*4882a593Smuzhiyun #define VME_AM_DATA 0x10 119*4882a593Smuzhiyun #define VME_AM_PROG 0x20 120*4882a593Smuzhiyun #define VME_AM_Mxx 0x30 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define VME_FLAG_D8 0x01 123*4882a593Smuzhiyun #define VME_FLAG_D16 0x02 124*4882a593Smuzhiyun #define VME_FLAG_D32 0x03 125*4882a593Smuzhiyun #define VME_FLAG_Dxx 0x03 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define PCI_MS_MEM 0x01 128*4882a593Smuzhiyun #define PCI_MS_IO 0x02 129*4882a593Smuzhiyun #define PCI_MS_CONFIG 0x03 130*4882a593Smuzhiyun #define PCI_MS_Mxx 0x03 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #endif 133