1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2009 Wind River Systems, Inc.
3*4882a593Smuzhiyun * Tom Rix <Tom.Rix at windriver.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Derived from code on omapzoom, git://git.omapzoom.com/repo/u-boot.git
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright (C) 2007-2009 Texas Instruments, Inc.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #ifndef TWL4030_H
13*4882a593Smuzhiyun #define TWL4030_H
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <common.h>
16*4882a593Smuzhiyun #include <i2c.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* I2C chip addresses */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* USB */
21*4882a593Smuzhiyun #define TWL4030_CHIP_USB 0x48
22*4882a593Smuzhiyun /* AUD */
23*4882a593Smuzhiyun #define TWL4030_CHIP_AUDIO_VOICE 0x49
24*4882a593Smuzhiyun #define TWL4030_CHIP_GPIO 0x49
25*4882a593Smuzhiyun #define TWL4030_CHIP_INTBR 0x49
26*4882a593Smuzhiyun #define TWL4030_CHIP_PIH 0x49
27*4882a593Smuzhiyun #define TWL4030_CHIP_TEST 0x49
28*4882a593Smuzhiyun /* AUX */
29*4882a593Smuzhiyun #define TWL4030_CHIP_KEYPAD 0x4a
30*4882a593Smuzhiyun #define TWL4030_CHIP_MADC 0x4a
31*4882a593Smuzhiyun #define TWL4030_CHIP_INTERRUPTS 0x4a
32*4882a593Smuzhiyun #define TWL4030_CHIP_LED 0x4a
33*4882a593Smuzhiyun #define TWL4030_CHIP_MAIN_CHARGE 0x4a
34*4882a593Smuzhiyun #define TWL4030_CHIP_PRECHARGE 0x4a
35*4882a593Smuzhiyun #define TWL4030_CHIP_PWM0 0x4a
36*4882a593Smuzhiyun #define TWL4030_CHIP_PWM1 0x4a
37*4882a593Smuzhiyun #define TWL4030_CHIP_PWMA 0x4a
38*4882a593Smuzhiyun #define TWL4030_CHIP_PWMB 0x4a
39*4882a593Smuzhiyun /* POWER */
40*4882a593Smuzhiyun #define TWL4030_CHIP_BACKUP 0x4b
41*4882a593Smuzhiyun #define TWL4030_CHIP_INT 0x4b
42*4882a593Smuzhiyun #define TWL4030_CHIP_PM_MASTER 0x4b
43*4882a593Smuzhiyun #define TWL4030_CHIP_PM_RECEIVER 0x4b
44*4882a593Smuzhiyun #define TWL4030_CHIP_RTC 0x4b
45*4882a593Smuzhiyun #define TWL4030_CHIP_SECURED_REG 0x4b
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* Register base addresses */
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* USB */
50*4882a593Smuzhiyun #define TWL4030_BASEADD_USB 0x0000
51*4882a593Smuzhiyun /* AUD */
52*4882a593Smuzhiyun #define TWL4030_BASEADD_AUDIO_VOICE 0x0000
53*4882a593Smuzhiyun #define TWL4030_BASEADD_GPIO 0x0098
54*4882a593Smuzhiyun #define TWL4030_BASEADD_INTBR 0x0085
55*4882a593Smuzhiyun #define TWL4030_BASEADD_PIH 0x0080
56*4882a593Smuzhiyun #define TWL4030_BASEADD_TEST 0x004C
57*4882a593Smuzhiyun /* AUX */
58*4882a593Smuzhiyun #define TWL4030_BASEADD_INTERRUPTS 0x00B9
59*4882a593Smuzhiyun #define TWL4030_BASEADD_LED 0x00EE
60*4882a593Smuzhiyun #define TWL4030_BASEADD_MADC 0x0000
61*4882a593Smuzhiyun #define TWL4030_BASEADD_MAIN_CHARGE 0x0074
62*4882a593Smuzhiyun #define TWL4030_BASEADD_PRECHARGE 0x00AA
63*4882a593Smuzhiyun #define TWL4030_BASEADD_PWM0 0x00F8
64*4882a593Smuzhiyun #define TWL4030_BASEADD_PWM1 0x00FB
65*4882a593Smuzhiyun #define TWL4030_BASEADD_PWMA 0x00EF
66*4882a593Smuzhiyun #define TWL4030_BASEADD_PWMB 0x00F1
67*4882a593Smuzhiyun #define TWL4030_BASEADD_KEYPAD 0x00D2
68*4882a593Smuzhiyun /* POWER */
69*4882a593Smuzhiyun #define TWL4030_BASEADD_BACKUP 0x0014
70*4882a593Smuzhiyun #define TWL4030_BASEADD_INT 0x002E
71*4882a593Smuzhiyun #define TWL4030_BASEADD_PM_MASTER 0x0036
72*4882a593Smuzhiyun #define TWL4030_BASEADD_PM_RECIEVER 0x005B
73*4882a593Smuzhiyun #define TWL4030_BASEADD_RTC 0x001C
74*4882a593Smuzhiyun #define TWL4030_BASEADD_SECURED_REG 0x0000
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /*
77*4882a593Smuzhiyun * Power Management Master
78*4882a593Smuzhiyun */
79*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x36
80*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x37
81*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x38
82*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x39
83*4882a593Smuzhiyun #define TWL4030_PM_MASTER_STS_BOOT 0x3A
84*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_BOOT 0x3B
85*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SHUNDAN 0x3C
86*4882a593Smuzhiyun #define TWL4030_PM_MASTER_BOOT_BCI 0x3D
87*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_PWRANA1 0x3E
88*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_PWRANA2 0x3F
89*4882a593Smuzhiyun #define TWL4030_PM_MASTER_BGAP_TRIM 0x40
90*4882a593Smuzhiyun #define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x41
91*4882a593Smuzhiyun #define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x42
92*4882a593Smuzhiyun #define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x43
93*4882a593Smuzhiyun #define TWL4030_PM_MASTER_PROTECT_KEY 0x44
94*4882a593Smuzhiyun #define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x45
95*4882a593Smuzhiyun #define TWL4030_PM_MASTER_P1_SW_EVENTS 0x46
96*4882a593Smuzhiyun #define TWL4030_PM_MASTER_P2_SW_EVENTS 0x47
97*4882a593Smuzhiyun #define TWL4030_PM_MASTER_P3_SW_EVENTS 0x48
98*4882a593Smuzhiyun #define TWL4030_PM_MASTER_STS_P123_STATE 0x49
99*4882a593Smuzhiyun #define TWL4030_PM_MASTER_PB_CFG 0x4A
100*4882a593Smuzhiyun #define TWL4030_PM_MASTER_PB_WORD_MSB 0x4B
101*4882a593Smuzhiyun #define TWL4030_PM_MASTER_PB_WORD_LSB 0x4C
102*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x52
103*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x53
104*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x54
105*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x55
106*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x56
107*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x57
108*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x58
109*4882a593Smuzhiyun #define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x59
110*4882a593Smuzhiyun #define TWL4030_PM_MASTER_MEMORY_DATA 0x5A
111*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SC_CONFIG 0x5B
112*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SC_DETECT1 0x5C
113*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SC_DETECT2 0x5D
114*4882a593Smuzhiyun #define TWL4030_PM_MASTER_WATCHDOG_CFG 0x5E
115*4882a593Smuzhiyun #define TWL4030_PM_MASTER_IT_CHECK_CFG 0x5F
116*4882a593Smuzhiyun #define TWL4030_PM_MASTER_VIBRATOR_CFG 0x60
117*4882a593Smuzhiyun #define TWL4030_PM_MASTER_DCDC_GLOBAL_CFG 0x61
118*4882a593Smuzhiyun #define TWL4030_PM_MASTER_VDD1_TRIM1 0x62
119*4882a593Smuzhiyun #define TWL4030_PM_MASTER_VDD1_TRIM2 0x63
120*4882a593Smuzhiyun #define TWL4030_PM_MASTER_VDD2_TRIM1 0x64
121*4882a593Smuzhiyun #define TWL4030_PM_MASTER_VDD2_TRIM2 0x65
122*4882a593Smuzhiyun #define TWL4030_PM_MASTER_VIO_TRIM1 0x66
123*4882a593Smuzhiyun #define TWL4030_PM_MASTER_VIO_TRIM2 0x67
124*4882a593Smuzhiyun #define TWL4030_PM_MASTER_MISC_CFG 0x68
125*4882a593Smuzhiyun #define TWL4030_PM_MASTER_LS_TST_A 0x69
126*4882a593Smuzhiyun #define TWL4030_PM_MASTER_LS_TST_B 0x6A
127*4882a593Smuzhiyun #define TWL4030_PM_MASTER_LS_TST_C 0x6B
128*4882a593Smuzhiyun #define TWL4030_PM_MASTER_LS_TST_D 0x6C
129*4882a593Smuzhiyun #define TWL4030_PM_MASTER_BB_CFG 0x6D
130*4882a593Smuzhiyun #define TWL4030_PM_MASTER_MISC_TST 0x6E
131*4882a593Smuzhiyun #define TWL4030_PM_MASTER_TRIM1 0x6F
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /* Power bus message definitions */
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /* The TWL4030/5030 splits its power-management resources (the various
136*4882a593Smuzhiyun * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
137*4882a593Smuzhiyun * P3. These groups can then be configured to transition between sleep, wait-on
138*4882a593Smuzhiyun * and active states by sending messages to the power bus. See Section 5.4.2
139*4882a593Smuzhiyun * Power Resources of TWL4030 TRM
140*4882a593Smuzhiyun */
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* Processor groups */
143*4882a593Smuzhiyun #define DEV_GRP_NULL 0x0
144*4882a593Smuzhiyun #define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
145*4882a593Smuzhiyun #define DEV_GRP_P2 0x2 /* P2: all Modem devices */
146*4882a593Smuzhiyun #define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /* Resource groups */
149*4882a593Smuzhiyun #define RES_GRP_RES 0x0 /* Reserved */
150*4882a593Smuzhiyun #define RES_GRP_PP 0x1 /* Power providers */
151*4882a593Smuzhiyun #define RES_GRP_RC 0x2 /* Reset and control */
152*4882a593Smuzhiyun #define RES_GRP_PP_RC 0x3
153*4882a593Smuzhiyun #define RES_GRP_PR 0x4 /* Power references */
154*4882a593Smuzhiyun #define RES_GRP_PP_PR 0x5
155*4882a593Smuzhiyun #define RES_GRP_RC_PR 0x6
156*4882a593Smuzhiyun #define RES_GRP_ALL 0x7 /* All resource groups */
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun #define RES_TYPE2_R0 0x0
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun #define RES_TYPE_ALL 0x7
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* Resource states */
163*4882a593Smuzhiyun #define RES_STATE_WRST 0xF
164*4882a593Smuzhiyun #define RES_STATE_ACTIVE 0xE
165*4882a593Smuzhiyun #define RES_STATE_SLEEP 0x8
166*4882a593Smuzhiyun #define RES_STATE_OFF 0x0
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun /* Power resources */
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun /* Power providers */
171*4882a593Smuzhiyun #define RES_VAUX1 1
172*4882a593Smuzhiyun #define RES_VAUX2 2
173*4882a593Smuzhiyun #define RES_VAUX3 3
174*4882a593Smuzhiyun #define RES_VAUX4 4
175*4882a593Smuzhiyun #define RES_VMMC1 5
176*4882a593Smuzhiyun #define RES_VMMC2 6
177*4882a593Smuzhiyun #define RES_VPLL1 7
178*4882a593Smuzhiyun #define RES_VPLL2 8
179*4882a593Smuzhiyun #define RES_VSIM 9
180*4882a593Smuzhiyun #define RES_VDAC 10
181*4882a593Smuzhiyun #define RES_VINTANA1 11
182*4882a593Smuzhiyun #define RES_VINTANA2 12
183*4882a593Smuzhiyun #define RES_VINTDIG 13
184*4882a593Smuzhiyun #define RES_VIO 14
185*4882a593Smuzhiyun #define RES_VDD1 15
186*4882a593Smuzhiyun #define RES_VDD2 16
187*4882a593Smuzhiyun #define RES_VUSB_1V5 17
188*4882a593Smuzhiyun #define RES_VUSB_1V8 18
189*4882a593Smuzhiyun #define RES_VUSB_3V1 19
190*4882a593Smuzhiyun #define RES_VUSBCP 20
191*4882a593Smuzhiyun #define RES_REGEN 21
192*4882a593Smuzhiyun /* Reset and control */
193*4882a593Smuzhiyun #define RES_NRES_PWRON 22
194*4882a593Smuzhiyun #define RES_CLKEN 23
195*4882a593Smuzhiyun #define RES_SYSEN 24
196*4882a593Smuzhiyun #define RES_HFCLKOUT 25
197*4882a593Smuzhiyun #define RES_32KCLKOUT 26
198*4882a593Smuzhiyun #define RES_RESET 27
199*4882a593Smuzhiyun /* Power Reference */
200*4882a593Smuzhiyun #define RES_Main_Ref 28
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun /* P[1-3]_SW_EVENTS */
203*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON (1 << 6)
204*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN (1 << 5)
205*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET (1 << 4)
206*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP (1 << 3)
207*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SW_EVENTS_DEVACT (1 << 2)
208*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1)
209*4882a593Smuzhiyun #define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0)
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun /* HW conditions */
212*4882a593Smuzhiyun #define TWL4030_PM_MASTER_STS_HW_CONDITIONS_PWON (1 << 0)
213*4882a593Smuzhiyun #define TWL4030_PM_MASTER_STS_HW_CONDITIONS_CHG (1 << 1)
214*4882a593Smuzhiyun #define TWL4030_PM_MASTER_STS_HW_CONDITIONS_USB (1 << 2)
215*4882a593Smuzhiyun #define TWL4030_PM_MASTER_STS_HW_CONDITIONS_VBUS (1 << 7)
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun /* Power transition */
218*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_PWON (1 << 0)
219*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_CHG (1 << 1)
220*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_USB (1 << 2)
221*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_RTC (1 << 3)
222*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT (1 << 4)
223*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBUS (1 << 5)
224*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_SWBUG (1 << 7)
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun /* PWRANA2 */
227*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT0_LOWV (1 << 1)
228*4882a593Smuzhiyun #define TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT1_LOWV (1 << 2)
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun #define TOTAL_RESOURCES 28
231*4882a593Smuzhiyun /*
232*4882a593Smuzhiyun * Power Bus Message Format ... these can be sent individually by Linux,
233*4882a593Smuzhiyun * but are usually part of downloaded scripts that are run when various
234*4882a593Smuzhiyun * power events are triggered.
235*4882a593Smuzhiyun *
236*4882a593Smuzhiyun * Broadcast Message (16 Bits):
237*4882a593Smuzhiyun * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
238*4882a593Smuzhiyun * RES_STATE[3:0]
239*4882a593Smuzhiyun *
240*4882a593Smuzhiyun * Singular Message (16 Bits):
241*4882a593Smuzhiyun * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
242*4882a593Smuzhiyun */
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun #define MSG_BROADCAST(devgrp, grp, type, type2, state) \
245*4882a593Smuzhiyun ((devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
246*4882a593Smuzhiyun | (type) << 4 | (state))
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun #define MSG_SINGULAR(devgrp, id, state) \
249*4882a593Smuzhiyun ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun #define MSG_BROADCAST_ALL(devgrp, state) \
252*4882a593Smuzhiyun ((devgrp) << 5 | (state))
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun #define MSG_BROADCAST_REF MSG_BROADCAST_ALL
255*4882a593Smuzhiyun #define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
256*4882a593Smuzhiyun #define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun /* Power Managment Receiver */
259*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_SC_CONFIG 0x5B
260*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_SC_DETECT1 0x5C
261*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_SC_DETECT2 0x5D
262*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_WATCHDOG_CFG 0x5E
263*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_IT_CHECK_CFG 0x5F
264*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VIBRATOR_CFG 0x5F
265*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_DC_TO_DC_CFG 0x61
266*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_TRIM1 0x62
267*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_TRIM2 0x63
268*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_TRIM1 0x64
269*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_TRIM2 0x65
270*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VIO_TRIM1 0x66
271*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VIO_TRIM2 0x67
272*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_MISC_CFG 0x68
273*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_LS_TST_A 0x69
274*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_LS_TST_B 0x6A
275*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_LS_TST_C 0x6B
276*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_LS_TST_D 0x6C
277*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_BB_CFG 0x6D
278*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_MISC_TST 0x6E
279*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_TRIM1 0x6F
280*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_TRIM2 0x70
281*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_DC_DC_TIMEOUT 0x71
282*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX1_DEV_GRP 0x72
283*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX1_TYPE 0x73
284*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX1_REMAP 0x74
285*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX1_DEDICATED 0x75
286*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX2_DEV_GRP 0x76
287*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX2_TYPE 0x77
288*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX2_REMAP 0x78
289*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX2_DEDICATED 0x79
290*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX3_DEV_GRP 0x7A
291*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX3_TYPE 0x7B
292*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX3_REMAP 0x7C
293*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX3_DEDICATED 0x7D
294*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX4_DEV_GRP 0x7E
295*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX4_TYPE 0x7F
296*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX4_REMAP 0x80
297*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX4_DEDICATED 0x81
298*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VMMC1_DEV_GRP 0x82
299*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VMMC1_TYPE 0x83
300*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VMMC1_REMAP 0x84
301*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VMMC1_DEDICATED 0x85
302*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VMMC2_DEV_GRP 0x86
303*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VMMC2_TYPE 0x87
304*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VMMC2_REMAP 0x88
305*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VMMC2_DEDICATED 0x89
306*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VPLL1_DEV_GRP 0x8A
307*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VPLL1_TYPE 0x8B
308*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VPLL1_REMAP 0x8C
309*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VPLL1_DEDICATED 0x8D
310*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VPLL2_DEV_GRP 0x8E
311*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VPLL2_TYPE 0x8F
312*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VPLL2_REMAP 0x90
313*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VPLL2_DEDICATED 0x91
314*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VSIM_DEV_GRP 0x92
315*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VSIM_TYPE 0x93
316*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VSIM_REMAP 0x94
317*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VSIM_DEDICATED 0x95
318*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDAC_DEV_GRP 0x96
319*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDAC_TYPE 0x97
320*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDAC_REMAP 0x98
321*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDAC_DEDICATED 0x99
322*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VINTANA1_DEV_GRP 0x9A
323*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VINTANA1_TYP 0x9B
324*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VINTANA1_REMAP 0x9C
325*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VINTANA1_DEDICATED 0x9D
326*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VINTANA2_DEV_GRP 0x9E
327*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VINTANA2_TYPE 0x9F
328*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VINTANA2_REMAP 0xA0
329*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VINTANA2_DEDICATED 0xA1
330*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VINTDIG_DEV_GRP 0xA2
331*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VINTDIG_TYPE 0xA3
332*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VINTDIG_REMAP 0xA4
333*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VINTDIG_DEDICATED 0xA5
334*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VIO_DEV_GRP 0xA6
335*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VIO_TYPE 0xA7
336*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VIO_REMAP 0xA8
337*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VIO_CFG 0xA9
338*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VIO_MISC_CFG 0xAA
339*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VIO_TEST1 0xAB
340*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VIO_TEST2 0xAC
341*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VIO_OSC 0xAD
342*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VIO_RESERVED 0xAE
343*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VIO_VSEL 0xAF
344*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_DEV_GRP 0xB0
345*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_TYPE 0xB1
346*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_REMAP 0xB2
347*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_CFG 0xB3
348*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_MISC_CFG 0xB4
349*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_TEST1 0xB5
350*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_TEST2 0xB6
351*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_OSC 0xB7
352*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_RESERVED 0xB8
353*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_VSEL 0xB9
354*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_VMODE_CFG 0xBA
355*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_VFLOOR 0xBB
356*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_VROOF 0xBC
357*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD1_STEP 0xBD
358*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_DEV_GRP 0xBE
359*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_TYPE 0xBF
360*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_REMAP 0xC0
361*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_CFG 0xC1
362*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_MISC_CFG 0xC2
363*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_TEST1 0xC3
364*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_TEST2 0xC4
365*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_OSC 0xC5
366*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_RESERVED 0xC6
367*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_VSEL 0xC7
368*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_VMODE_CFG 0xC8
369*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_VFLOOR 0xC9
370*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_VROOF 0xCA
371*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDD2_STEP 0xCB
372*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP 0xCC
373*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VUSB1V5_TYPE 0xCD
374*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VUSB1V5_REMAP 0xCE
375*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP 0xCF
376*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VUSB1V8_TYPE 0xD0
377*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VUSB1V8_REMAP 0xD1
378*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP 0xD2
379*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VUSB3V1_TYPE 0xD3
380*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VUSB3V1_REMAP 0xD4
381*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VUSBCP_DEV_GRP 0xD5
382*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VUSBCP_TYPE 0xD6
383*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VUSBCP_REMAP 0xD7
384*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VUSB_DEDICATED1 0xD8
385*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VUSB_DEDICATED2 0xD9
386*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_REGEN_DEV_GRP 0xDA
387*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_REGEN_TYPE 0xDB
388*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_REGEN_REMAP 0xDC
389*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_NRESPWRON_DEV_GRP 0xDD
390*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_NRESPWRON_TYPE 0xDE
391*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_NRESPWRON_REMAP 0xDF
392*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_CLKEN_DEV_GRP 0xE0
393*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_CLKEN_TYPE 0xE1
394*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_CLKEN_REMAP 0xE2
395*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_SYSEN_DEV_GRP 0xE3
396*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_SYSEN_TYPE 0xE4
397*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_SYSEN_REMAP 0xE5
398*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_HFCLKOUT_DEV_GRP 0xE6
399*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_HFCLKOUT_TYPE 0xE7
400*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_HFCLKOUT_REMAP 0xE8
401*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_32KCLKOUT_DEV_GRP 0xE9
402*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_32KCLKOUT_TYPE 0xEA
403*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_32KCLKOUT_REMAP 0xEB
404*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_TRITON_RESET_DEV_GRP 0xEC
405*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_TRITON_RESET_TYPE 0xED
406*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_TRITON_RESET_REMAP 0xEE
407*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_MAINREF_DEV_GRP 0xEF
408*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_MAINREF_TYPE 0xF0
409*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_MAINREF_REMAP 0xF1
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun /* Voltage Selection in PM Receiver Module */
412*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX2_VSEL_18 0x05
413*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX2_VSEL_28 0x09
414*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX3_VSEL_18 0x01
415*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VAUX3_VSEL_28 0x03
416*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VPLL2_VSEL_18 0x05
417*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03
418*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02
419*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VMMC1_VSEL_32 0x03
420*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VMMC2_VSEL_30 0x0B
421*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VMMC2_VSEL_32 0x0C
422*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_VSIM_VSEL_18 0x03
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun /* Device Selection in PM Receiver Module */
425*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_DEV_GRP_P1 0x20
426*4882a593Smuzhiyun #define TWL4030_PM_RECEIVER_DEV_GRP_ALL 0xE0
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun /* LED */
429*4882a593Smuzhiyun #define TWL4030_LED_LEDEN 0xEE
430*4882a593Smuzhiyun #define TWL4030_LED_LEDEN_LEDAON (1 << 0)
431*4882a593Smuzhiyun #define TWL4030_LED_LEDEN_LEDBON (1 << 1)
432*4882a593Smuzhiyun #define TWL4030_LED_LEDEN_LEDAPWM (1 << 4)
433*4882a593Smuzhiyun #define TWL4030_LED_LEDEN_LEDBPWM (1 << 5)
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun /* Keypad */
436*4882a593Smuzhiyun #define TWL4030_KEYPAD_KEYP_CTRL_REG 0xD2
437*4882a593Smuzhiyun #define TWL4030_KEYPAD_KEY_DEB_REG 0xD3
438*4882a593Smuzhiyun #define TWL4030_KEYPAD_LONG_KEY_REG1 0xD4
439*4882a593Smuzhiyun #define TWL4030_KEYPAD_LK_PTV_REG 0xD5
440*4882a593Smuzhiyun #define TWL4030_KEYPAD_TIME_OUT_REG1 0xD6
441*4882a593Smuzhiyun #define TWL4030_KEYPAD_TIME_OUT_REG2 0xD7
442*4882a593Smuzhiyun #define TWL4030_KEYPAD_KBC_REG 0xD8
443*4882a593Smuzhiyun #define TWL4030_KEYPAD_KBR_REG 0xD9
444*4882a593Smuzhiyun #define TWL4030_KEYPAD_KEYP_SMS 0xDA
445*4882a593Smuzhiyun #define TWL4030_KEYPAD_FULL_CODE_7_0 0xDB
446*4882a593Smuzhiyun #define TWL4030_KEYPAD_FULL_CODE_15_8 0xDC
447*4882a593Smuzhiyun #define TWL4030_KEYPAD_FULL_CODE_23_16 0xDD
448*4882a593Smuzhiyun #define TWL4030_KEYPAD_FULL_CODE_31_24 0xDE
449*4882a593Smuzhiyun #define TWL4030_KEYPAD_FULL_CODE_39_32 0xDF
450*4882a593Smuzhiyun #define TWL4030_KEYPAD_FULL_CODE_47_40 0xE0
451*4882a593Smuzhiyun #define TWL4030_KEYPAD_FULL_CODE_55_48 0xE1
452*4882a593Smuzhiyun #define TWL4030_KEYPAD_FULL_CODE_63_56 0xE2
453*4882a593Smuzhiyun #define TWL4030_KEYPAD_KEYP_ISR1 0xE3
454*4882a593Smuzhiyun #define TWL4030_KEYPAD_KEYP_IMR1 0xE4
455*4882a593Smuzhiyun #define TWL4030_KEYPAD_KEYP_ISR2 0xE5
456*4882a593Smuzhiyun #define TWL4030_KEYPAD_KEYP_IMR2 0xE6
457*4882a593Smuzhiyun #define TWL4030_KEYPAD_KEYP_SIR 0xE7
458*4882a593Smuzhiyun #define TWL4030_KEYPAD_KEYP_EDR 0xE8
459*4882a593Smuzhiyun #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0xE9
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun #define TWL4030_KEYPAD_CTRL_KBD_ON (1 << 6)
462*4882a593Smuzhiyun #define TWL4030_KEYPAD_CTRL_RP_EN (1 << 5)
463*4882a593Smuzhiyun #define TWL4030_KEYPAD_CTRL_TOLE_EN (1 << 4)
464*4882a593Smuzhiyun #define TWL4030_KEYPAD_CTRL_TOE_EN (1 << 3)
465*4882a593Smuzhiyun #define TWL4030_KEYPAD_CTRL_LK_EN (1 << 2)
466*4882a593Smuzhiyun #define TWL4030_KEYPAD_CTRL_SOFTMODEN (1 << 1)
467*4882a593Smuzhiyun #define TWL4030_KEYPAD_CTRL_SOFT_NRST (1 << 0)
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun /* USB */
470*4882a593Smuzhiyun #define TWL4030_USB_VENDOR_ID_LO 0x00
471*4882a593Smuzhiyun #define TWL4030_USB_VENDOR_ID_HI 0x01
472*4882a593Smuzhiyun #define TWL4030_USB_PRODUCT_ID_LO 0x02
473*4882a593Smuzhiyun #define TWL4030_USB_PRODUCT_ID_HI 0x03
474*4882a593Smuzhiyun #define TWL4030_USB_FUNC_CTRL 0x04
475*4882a593Smuzhiyun #define TWL4030_USB_FUNC_CTRL_SET 0x05
476*4882a593Smuzhiyun #define TWL4030_USB_FUNC_CTRL_CLR 0x06
477*4882a593Smuzhiyun #define TWL4030_USB_IFC_CTRL 0x07
478*4882a593Smuzhiyun #define TWL4030_USB_IFC_CTRL_SET 0x08
479*4882a593Smuzhiyun #define TWL4030_USB_IFC_CTRL_CLR 0x09
480*4882a593Smuzhiyun #define TWL4030_USB_OTG_CTRL 0x0A
481*4882a593Smuzhiyun #define TWL4030_USB_OTG_CTRL_SET 0x0B
482*4882a593Smuzhiyun #define TWL4030_USB_OTG_CTRL_CLR 0x0C
483*4882a593Smuzhiyun #define TWL4030_USB_USB_INT_EN_RISE 0x0D
484*4882a593Smuzhiyun #define TWL4030_USB_USB_INT_EN_RISE_SET 0x0E
485*4882a593Smuzhiyun #define TWL4030_USB_USB_INT_EN_RISE_CLR 0x0F
486*4882a593Smuzhiyun #define TWL4030_USB_USB_INT_EN_FALL 0x10
487*4882a593Smuzhiyun #define TWL4030_USB_USB_INT_EN_FALL_SET 0x11
488*4882a593Smuzhiyun #define TWL4030_USB_USB_INT_EN_FALL_CLR 0x12
489*4882a593Smuzhiyun #define TWL4030_USB_USB_INT_STS 0x13
490*4882a593Smuzhiyun #define TWL4030_USB_USB_INT_LATCH 0x14
491*4882a593Smuzhiyun #define TWL4030_USB_DEBUG 0x15
492*4882a593Smuzhiyun #define TWL4030_USB_SCRATCH_REG 0x16
493*4882a593Smuzhiyun #define TWL4030_USB_SCRATCH_REG_SET 0x17
494*4882a593Smuzhiyun #define TWL4030_USB_SCRATCH_REG_CLR 0x18
495*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_CTRL 0x19
496*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_CTRL_SET 0x1A
497*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_CTRL_CLR 0x1B
498*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_INT_DELAY 0x1C
499*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_INT_EN 0x1D
500*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_INT_EN_SET 0x1E
501*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_INT_EN_CLR 0x1F
502*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_INT_STS 0x20
503*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_INT_LATCH 0x21
504*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_PLS_CTRL 0x22
505*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_PLS_CTRL_SET 0x23
506*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_PLS_CTRL_CLR 0x24
507*4882a593Smuzhiyun #define TWL4030_USB_TRANS_POS_WIDTH 0x25
508*4882a593Smuzhiyun #define TWL4030_USB_TRANS_NEG_WIDTH 0x26
509*4882a593Smuzhiyun #define TWL4030_USB_RCV_PLTY_RECOVERY 0x27
510*4882a593Smuzhiyun #define TWL4030_USB_MCPC_CTRL 0x30
511*4882a593Smuzhiyun #define TWL4030_USB_MCPC_CTRL_SET 0x31
512*4882a593Smuzhiyun #define TWL4030_USB_MCPC_CTRL_CLR 0x32
513*4882a593Smuzhiyun #define TWL4030_USB_MCPC_IO_CTRL 0x33
514*4882a593Smuzhiyun #define TWL4030_USB_MCPC_IO_CTRL_SET 0x34
515*4882a593Smuzhiyun #define TWL4030_USB_MCPC_IO_CTRL_CLR 0x35
516*4882a593Smuzhiyun #define TWL4030_USB_MCPC_CTRL2 0x36
517*4882a593Smuzhiyun #define TWL4030_USB_MCPC_CTRL2_SET 0x37
518*4882a593Smuzhiyun #define TWL4030_USB_MCPC_CTRL2_CLR 0x38
519*4882a593Smuzhiyun #define TWL4030_USB_OTHER_FUNC_CTRL 0x80
520*4882a593Smuzhiyun #define TWL4030_USB_OTHER_FUNC_CTRL_SET 0x81
521*4882a593Smuzhiyun #define TWL4030_USB_OTHER_FUNC_CTRL_CLR 0x82
522*4882a593Smuzhiyun #define TWL4030_USB_OTHER_IFC_CTRL 0x83
523*4882a593Smuzhiyun #define TWL4030_USB_OTHER_IFC_CTRL_SET 0x84
524*4882a593Smuzhiyun #define TWL4030_USB_OTHER_IFC_CTRL_CLR 0x85
525*4882a593Smuzhiyun #define TWL4030_USB_OTHER_INT_EN_RISE_SET 0x87
526*4882a593Smuzhiyun #define TWL4030_USB_OTHER_INT_EN_RISE_CLR 0x88
527*4882a593Smuzhiyun #define TWL4030_USB_OTHER_INT_EN_FALL 0x89
528*4882a593Smuzhiyun #define TWL4030_USB_OTHER_INT_EN_FALL_SET 0x8A
529*4882a593Smuzhiyun #define TWL4030_USB_OTHER_INT_EN_FALL_CLR 0x8B
530*4882a593Smuzhiyun #define TWL4030_USB_OTHER_INT_STS 0x8C
531*4882a593Smuzhiyun #define TWL4030_USB_OTHER_INT_LATCH 0x8D
532*4882a593Smuzhiyun #define TWL4030_USB_ID_STATUS 0x96
533*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_1_INT_EN 0x97
534*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_1_INT_EN_SET 0x98
535*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_1_INT_EN_CLR 0x99
536*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_1_INT_STS 0x9A
537*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_1_INT_LATCH 0x9B
538*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_2_INT_EN 0x9C
539*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_2_INT_EN_SET 0x9D
540*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_2_INT_EN_CLR 0x9E
541*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_2_INT_STS 0x9F
542*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_2_INT_LATCH 0xA0
543*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_CTRL 0xA1
544*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_CTRL_SET 0xA2
545*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_CTRL_CLR 0xA3
546*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_CMD 0xA4
547*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_CMD_SET 0xA5
548*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_CMD_CLR 0xA6
549*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_CMD_STS 0xA7
550*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_STATUS 0xA8
551*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_ERR_STATUS 0xAA
552*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_SM_CTRL_STATE 0xAB
553*4882a593Smuzhiyun #define TWL4030_USB_POWER_CTRL 0xAC
554*4882a593Smuzhiyun #define TWL4030_USB_POWER_CTRL_SET 0xAD
555*4882a593Smuzhiyun #define TWL4030_USB_POWER_CTRL_CLR 0xAE
556*4882a593Smuzhiyun #define TWL4030_USB_OTHER_IFC_CTRL2 0xAF
557*4882a593Smuzhiyun #define TWL4030_USB_OTHER_IFC_CTRL2_SET 0xB0
558*4882a593Smuzhiyun #define TWL4030_USB_OTHER_IFC_CTRL2_CLR 0xB1
559*4882a593Smuzhiyun #define TWL4030_USB_REG_CTRL_EN 0xB2
560*4882a593Smuzhiyun #define TWL4030_USB_REG_CTRL_EN_SET 0xB3
561*4882a593Smuzhiyun #define TWL4030_USB_REG_CTRL_EN_CLR 0xB4
562*4882a593Smuzhiyun #define TWL4030_USB_REG_CTRL_ERROR 0xB5
563*4882a593Smuzhiyun #define TWL4030_USB_OTHER_FUNC_CTRL2 0xB8
564*4882a593Smuzhiyun #define TWL4030_USB_OTHER_FUNC_CTRL2_SET 0xB9
565*4882a593Smuzhiyun #define TWL4030_USB_OTHER_FUNC_CTRL2_CLR 0xBA
566*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_ANA_CTRL 0xBB
567*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_ANA_CTRL_SET 0xBC
568*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_ANA_CTRL_CLR 0xBD
569*4882a593Smuzhiyun #define TWL4030_USB_VBUS_DEBOUNCE 0xC0
570*4882a593Smuzhiyun #define TWL4030_USB_ID_DEBOUNCE 0xC1
571*4882a593Smuzhiyun #define TWL4030_USB_TPH_DP_CON_MIN 0xC2
572*4882a593Smuzhiyun #define TWL4030_USB_TPH_DP_CON_MAX 0xC3
573*4882a593Smuzhiyun #define TWL4030_USB_TCR_DP_CON_MIN 0xC4
574*4882a593Smuzhiyun #define TWL4030_USB_TCR_DP_CON_MAX 0xC5
575*4882a593Smuzhiyun #define TWL4030_USB_TPH_DP_PD_SHORT 0xC6
576*4882a593Smuzhiyun #define TWL4030_USB_TPH_CMD_DLY 0xC7
577*4882a593Smuzhiyun #define TWL4030_USB_TPH_DET_RST 0xC8
578*4882a593Smuzhiyun #define TWL4030_USB_TPH_AUD_BIAS 0xC9
579*4882a593Smuzhiyun #define TWL4030_USB_TCR_UART_DET_MIN 0xCA
580*4882a593Smuzhiyun #define TWL4030_USB_TCR_UART_DET_MAX 0xCB
581*4882a593Smuzhiyun #define TWL4030_USB_TPH_ID_INT_PW 0xCD
582*4882a593Smuzhiyun #define TWL4030_USB_TACC_ID_INT_WAIT 0xCE
583*4882a593Smuzhiyun #define TWL4030_USB_TACC_ID_INT_PW 0xCF
584*4882a593Smuzhiyun #define TWL4030_USB_TPH_CMD_WAIT 0xD0
585*4882a593Smuzhiyun #define TWL4030_USB_TPH_ACK_WAIT 0xD1
586*4882a593Smuzhiyun #define TWL4030_USB_TPH_DP_DISC_DET 0xD2
587*4882a593Smuzhiyun #define TWL4030_USB_VBAT_TIMER 0xD3
588*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_4W_DEBUG 0xE0
589*4882a593Smuzhiyun #define TWL4030_USB_CARKIT_5W_DEBUG 0xE1
590*4882a593Smuzhiyun #define TWL4030_USB_PHY_PWR_CTRL 0xFD
591*4882a593Smuzhiyun #define TWL4030_USB_PHY_CLK_CTRL 0xFE
592*4882a593Smuzhiyun #define TWL4030_USB_PHY_CLK_CTRL_STS 0xFF
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun /* GPIO */
595*4882a593Smuzhiyun #define TWL4030_GPIO_GPIODATAIN1 0x00
596*4882a593Smuzhiyun #define TWL4030_GPIO_GPIODATAIN2 0x01
597*4882a593Smuzhiyun #define TWL4030_GPIO_GPIODATAIN3 0x02
598*4882a593Smuzhiyun #define TWL4030_GPIO_GPIODATADIR1 0x03
599*4882a593Smuzhiyun #define TWL4030_GPIO_GPIODATADIR2 0x04
600*4882a593Smuzhiyun #define TWL4030_GPIO_GPIODATADIR3 0x05
601*4882a593Smuzhiyun #define TWL4030_GPIO_GPIODATAOUT1 0x06
602*4882a593Smuzhiyun #define TWL4030_GPIO_GPIODATAOUT2 0x07
603*4882a593Smuzhiyun #define TWL4030_GPIO_GPIODATAOUT3 0x08
604*4882a593Smuzhiyun #define TWL4030_GPIO_CLEARGPIODATAOUT1 0x09
605*4882a593Smuzhiyun #define TWL4030_GPIO_CLEARGPIODATAOUT2 0x0A
606*4882a593Smuzhiyun #define TWL4030_GPIO_CLEARGPIODATAOUT3 0x0B
607*4882a593Smuzhiyun #define TWL4030_GPIO_SETGPIODATAOUT1 0x0C
608*4882a593Smuzhiyun #define TWL4030_GPIO_SETGPIODATAOUT2 0x0D
609*4882a593Smuzhiyun #define TWL4030_GPIO_SETGPIODATAOUT3 0x0E
610*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_DEBEN1 0x0F
611*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_DEBEN2 0x10
612*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_DEBEN3 0x11
613*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_CTRL 0x12
614*4882a593Smuzhiyun #define TWL4030_GPIO_GPIOPUPDCTR1 0x13
615*4882a593Smuzhiyun #define TWL4030_GPIO_GPIOPUPDCTR2 0x14
616*4882a593Smuzhiyun #define TWL4030_GPIO_GPIOPUPDCTR3 0x15
617*4882a593Smuzhiyun #define TWL4030_GPIO_GPIOPUPDCTR4 0x16
618*4882a593Smuzhiyun #define TWL4030_GPIO_GPIOPUPDCTR5 0x17
619*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_ISR1A 0x19
620*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_ISR2A 0x1A
621*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_ISR3A 0x1B
622*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_IMR1A 0x1C
623*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_IMR2A 0x1D
624*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_IMR3A 0x1E
625*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_ISR1B 0x1F
626*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_ISR2B 0x20
627*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_ISR3B 0x21
628*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_IMR1B 0x22
629*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_IMR2B 0x23
630*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_IMR3B 0x24
631*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_EDR1 0x28
632*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_EDR2 0x29
633*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_EDR3 0x2A
634*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_EDR4 0x2B
635*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_EDR5 0x2C
636*4882a593Smuzhiyun #define TWL4030_GPIO_GPIO_SIH_CTRL 0x2D
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun /*
639*4882a593Smuzhiyun * Convience functions to read and write from TWL4030
640*4882a593Smuzhiyun *
641*4882a593Smuzhiyun * chip_no is the i2c address, it must be one of the chip addresses
642*4882a593Smuzhiyun * defined at the top of this file with the prefix TWL4030_CHIP_
643*4882a593Smuzhiyun * examples are TWL4030_CHIP_PM_RECEIVER and TWL4030_CHIP_KEYPAD
644*4882a593Smuzhiyun *
645*4882a593Smuzhiyun * val is the data either written to or read from the twl4030
646*4882a593Smuzhiyun *
647*4882a593Smuzhiyun * reg is the register to act on, it must be one of the defines
648*4882a593Smuzhiyun * above and with the format TWL4030_<chip suffix>_<register name>
649*4882a593Smuzhiyun * examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and
650*4882a593Smuzhiyun * TWL4030_LED_LEDEN.
651*4882a593Smuzhiyun */
twl4030_i2c_write_u8(u8 chip_no,u8 reg,u8 val)652*4882a593Smuzhiyun static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
653*4882a593Smuzhiyun {
654*4882a593Smuzhiyun return i2c_write(chip_no, reg, 1, &val, 1);
655*4882a593Smuzhiyun }
656*4882a593Smuzhiyun
twl4030_i2c_read_u8(u8 chip_no,u8 reg,u8 * val)657*4882a593Smuzhiyun static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
658*4882a593Smuzhiyun {
659*4882a593Smuzhiyun return i2c_read(chip_no, reg, 1, val, 1);
660*4882a593Smuzhiyun }
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun /*
663*4882a593Smuzhiyun * Power
664*4882a593Smuzhiyun */
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun /* For hardware resetting */
667*4882a593Smuzhiyun void twl4030_power_reset_init(void);
668*4882a593Smuzhiyun /* For power off */
669*4882a593Smuzhiyun void twl4030_power_off(void);
670*4882a593Smuzhiyun /* For setting device group and voltage */
671*4882a593Smuzhiyun void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
672*4882a593Smuzhiyun u8 dev_grp, u8 dev_grp_sel);
673*4882a593Smuzhiyun /* For initializing power device */
674*4882a593Smuzhiyun void twl4030_power_init(void);
675*4882a593Smuzhiyun /* For initializing mmc power */
676*4882a593Smuzhiyun void twl4030_power_mmc_init(int dev_index);
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun /*
679*4882a593Smuzhiyun * Input
680*4882a593Smuzhiyun */
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun int twl4030_input_power_button(void);
683*4882a593Smuzhiyun int twl4030_input_charger(void);
684*4882a593Smuzhiyun int twl4030_input_usb(void);
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun int twl4030_keypad_scan(unsigned char *matrix);
687*4882a593Smuzhiyun int twl4030_keypad_key(unsigned char *matrix, u8 c, u8 r);
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun /*
690*4882a593Smuzhiyun * LED
691*4882a593Smuzhiyun */
692*4882a593Smuzhiyun void twl4030_led_init(unsigned char ledon_mask);
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun /*
695*4882a593Smuzhiyun * USB
696*4882a593Smuzhiyun */
697*4882a593Smuzhiyun int twl4030_usb_ulpi_init(void);
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun #endif /* TWL4030_H */
700