1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) Copyright 2023 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _SPL_DISPLAY_H_ 8*4882a593Smuzhiyun #define _SPL_DISPLAY_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <drm_modes.h> 12*4882a593Smuzhiyun #include <mp_boot.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* SPL display */ 15*4882a593Smuzhiyun #define RK3528_VOP_BASE 0xff840000 16*4882a593Smuzhiyun #define RK3528_HDMI_BASE 0xff8d0000 17*4882a593Smuzhiyun #define RK3528_HDMIPHY_BASE 0xffe00000 18*4882a593Smuzhiyun #define RK3528_CRU_BASE 0xff4a0000 19*4882a593Smuzhiyun #define RK3528_GPIO0_IOC_BASE 0xff540000 20*4882a593Smuzhiyun #define RK3528_GPIO_BASE 0xff610000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct spl_display_info { 23*4882a593Smuzhiyun struct drm_display_mode mode; 24*4882a593Smuzhiyun u32 bus_format; 25*4882a593Smuzhiyun u32 enabled; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun #endif 28*4882a593Smuzhiyun 29