1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2003 Arabella Software Ltd. 3*4882a593Smuzhiyun * Yuli Barcohen <yuli@arabellasw.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Serial Presence Detect (SPD) EEPROM format according to the 6*4882a593Smuzhiyun * Intel's PC SDRAM Serial Presence Detect (SPD) Specification, 7*4882a593Smuzhiyun * revision 1.2B, November 1999 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _SPD_H_ 13*4882a593Smuzhiyun #define _SPD_H_ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun typedef struct spd_eeprom_s { 16*4882a593Smuzhiyun unsigned char info_size; /* 0 # bytes written into serial memory */ 17*4882a593Smuzhiyun unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ 18*4882a593Smuzhiyun unsigned char mem_type; /* 2 Fundamental memory type */ 19*4882a593Smuzhiyun unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ 20*4882a593Smuzhiyun unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ 21*4882a593Smuzhiyun unsigned char nrows; /* 5 # of Module Rows on this assembly */ 22*4882a593Smuzhiyun unsigned char dataw_lsb; /* 6 Data Width of this assembly */ 23*4882a593Smuzhiyun unsigned char dataw_msb; /* 7 ... Data Width continuation */ 24*4882a593Smuzhiyun unsigned char voltage; /* 8 Voltage intf std of this assembly */ 25*4882a593Smuzhiyun unsigned char clk_cycle; /* 9 SDRAM Cycle time at CL=X */ 26*4882a593Smuzhiyun unsigned char clk_access; /* 10 SDRAM Access from Clock at CL=X */ 27*4882a593Smuzhiyun unsigned char config; /* 11 DIMM Configuration type */ 28*4882a593Smuzhiyun unsigned char refresh; /* 12 Refresh Rate/Type */ 29*4882a593Smuzhiyun unsigned char primw; /* 13 Primary SDRAM Width */ 30*4882a593Smuzhiyun unsigned char ecw; /* 14 Error Checking SDRAM width */ 31*4882a593Smuzhiyun unsigned char min_delay; /* 15 for Back to Back Random Address */ 32*4882a593Smuzhiyun unsigned char burstl; /* 16 Burst Lengths Supported */ 33*4882a593Smuzhiyun unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */ 34*4882a593Smuzhiyun unsigned char cas_lat; /* 18 CAS# Latencies Supported */ 35*4882a593Smuzhiyun unsigned char cs_lat; /* 19 CS# Latency */ 36*4882a593Smuzhiyun unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */ 37*4882a593Smuzhiyun unsigned char mod_attr; /* 21 SDRAM Module Attributes */ 38*4882a593Smuzhiyun unsigned char dev_attr; /* 22 SDRAM Device Attributes */ 39*4882a593Smuzhiyun unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time at CL=X-1 */ 40*4882a593Smuzhiyun unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */ 41*4882a593Smuzhiyun unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time at CL=X-2 */ 42*4882a593Smuzhiyun unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */ 43*4882a593Smuzhiyun unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ 44*4882a593Smuzhiyun unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ 45*4882a593Smuzhiyun unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ 46*4882a593Smuzhiyun unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ 47*4882a593Smuzhiyun unsigned char row_dens; /* 31 Density of each row on module */ 48*4882a593Smuzhiyun unsigned char ca_setup; /* 32 Cmd + Addr signal input setup time */ 49*4882a593Smuzhiyun unsigned char ca_hold; /* 33 Cmd and Addr signal input hold time */ 50*4882a593Smuzhiyun unsigned char data_setup; /* 34 Data signal input setup time */ 51*4882a593Smuzhiyun unsigned char data_hold; /* 35 Data signal input hold time */ 52*4882a593Smuzhiyun unsigned char twr; /* 36 Write Recovery time tWR */ 53*4882a593Smuzhiyun unsigned char twtr; /* 37 Int write to read delay tWTR */ 54*4882a593Smuzhiyun unsigned char trtp; /* 38 Int read to precharge delay tRTP */ 55*4882a593Smuzhiyun unsigned char mem_probe; /* 39 Mem analysis probe characteristics */ 56*4882a593Smuzhiyun unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */ 57*4882a593Smuzhiyun unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ 58*4882a593Smuzhiyun unsigned char trfc; /* 42 Min Auto to Active period tRFC */ 59*4882a593Smuzhiyun unsigned char tckmax; /* 43 Max device cycle time tCKmax */ 60*4882a593Smuzhiyun unsigned char tdqsq; /* 44 Max DQS to DQ skew */ 61*4882a593Smuzhiyun unsigned char tqhs; /* 45 Max Read DataHold skew tQHS */ 62*4882a593Smuzhiyun unsigned char pll_relock; /* 46 PLL Relock time */ 63*4882a593Smuzhiyun unsigned char res[15]; /* 47-xx IDD in SPD and Reserved space */ 64*4882a593Smuzhiyun unsigned char spd_rev; /* 62 SPD Data Revision Code */ 65*4882a593Smuzhiyun unsigned char cksum; /* 63 Checksum for bytes 0-62 */ 66*4882a593Smuzhiyun unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-108E */ 67*4882a593Smuzhiyun unsigned char mloc; /* 72 Manufacturing Location */ 68*4882a593Smuzhiyun unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ 69*4882a593Smuzhiyun unsigned char rev[2]; /* 91 Revision Code */ 70*4882a593Smuzhiyun unsigned char mdate[2]; /* 93 Manufacturing Date */ 71*4882a593Smuzhiyun unsigned char sernum[4]; /* 95 Assembly Serial Number */ 72*4882a593Smuzhiyun unsigned char mspec[27]; /* 99 Manufacturer Specific Data */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * Open for Customer Use starting with byte 128. 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun unsigned char freq; /* 128 Intel spec: frequency */ 78*4882a593Smuzhiyun unsigned char intel_cas; /* 129 Intel spec: CAS# Latency support */ 79*4882a593Smuzhiyun } spd_eeprom_t; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* 83*4882a593Smuzhiyun * Byte 2 Fundamental Memory Types. 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun #define SPD_MEMTYPE_FPM (0x01) 86*4882a593Smuzhiyun #define SPD_MEMTYPE_EDO (0x02) 87*4882a593Smuzhiyun #define SPD_MEMTYPE_PIPE_NIBBLE (0x03) 88*4882a593Smuzhiyun #define SPD_MEMTYPE_SDRAM (0x04) 89*4882a593Smuzhiyun #define SPD_MEMTYPE_ROM (0x05) 90*4882a593Smuzhiyun #define SPD_MEMTYPE_SGRAM (0x06) 91*4882a593Smuzhiyun #define SPD_MEMTYPE_DDR (0x07) 92*4882a593Smuzhiyun #define SPD_MEMTYPE_DDR2 (0x08) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #endif /* _SPD_H_ */ 95