1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2002 3*4882a593Smuzhiyun * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _SPARTAN3_H_ 9*4882a593Smuzhiyun #define _SPARTAN3_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <xilinx.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Slave Parallel Implementation function table */ 14*4882a593Smuzhiyun typedef struct { 15*4882a593Smuzhiyun xilinx_pre_fn pre; 16*4882a593Smuzhiyun xilinx_pgm_fn pgm; 17*4882a593Smuzhiyun xilinx_init_fn init; 18*4882a593Smuzhiyun xilinx_err_fn err; 19*4882a593Smuzhiyun xilinx_done_fn done; 20*4882a593Smuzhiyun xilinx_clk_fn clk; 21*4882a593Smuzhiyun xilinx_cs_fn cs; 22*4882a593Smuzhiyun xilinx_wr_fn wr; 23*4882a593Smuzhiyun xilinx_rdata_fn rdata; 24*4882a593Smuzhiyun xilinx_wdata_fn wdata; 25*4882a593Smuzhiyun xilinx_busy_fn busy; 26*4882a593Smuzhiyun xilinx_abort_fn abort; 27*4882a593Smuzhiyun xilinx_post_fn post; 28*4882a593Smuzhiyun } xilinx_spartan3_slave_parallel_fns; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* Slave Serial Implementation function table */ 31*4882a593Smuzhiyun typedef struct { 32*4882a593Smuzhiyun xilinx_pre_fn pre; 33*4882a593Smuzhiyun xilinx_pgm_fn pgm; 34*4882a593Smuzhiyun xilinx_clk_fn clk; 35*4882a593Smuzhiyun xilinx_init_fn init; 36*4882a593Smuzhiyun xilinx_done_fn done; 37*4882a593Smuzhiyun xilinx_wr_fn wr; 38*4882a593Smuzhiyun xilinx_post_fn post; 39*4882a593Smuzhiyun xilinx_bwr_fn bwr; /* block write function */ 40*4882a593Smuzhiyun xilinx_abort_fn abort; 41*4882a593Smuzhiyun } xilinx_spartan3_slave_serial_fns; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #if defined(CONFIG_FPGA_SPARTAN3) 44*4882a593Smuzhiyun extern struct xilinx_fpga_op spartan3_op; 45*4882a593Smuzhiyun # define FPGA_SPARTAN3_OPS &spartan3_op 46*4882a593Smuzhiyun #else 47*4882a593Smuzhiyun # define FPGA_SPARTAN3_OPS NULL 48*4882a593Smuzhiyun #endif 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Device Image Sizes 51*4882a593Smuzhiyun *********************************************************************/ 52*4882a593Smuzhiyun /* Spartan-III (1.2V) */ 53*4882a593Smuzhiyun #define XILINX_XC3S50_SIZE 439264/8 54*4882a593Smuzhiyun #define XILINX_XC3S200_SIZE 1047616/8 55*4882a593Smuzhiyun #define XILINX_XC3S400_SIZE 1699136/8 56*4882a593Smuzhiyun #define XILINX_XC3S1000_SIZE 3223488/8 57*4882a593Smuzhiyun #define XILINX_XC3S1500_SIZE 5214784/8 58*4882a593Smuzhiyun #define XILINX_XC3S2000_SIZE 7673024/8 59*4882a593Smuzhiyun #define XILINX_XC3S4000_SIZE 11316864/8 60*4882a593Smuzhiyun #define XILINX_XC3S5000_SIZE 13271936/8 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* Spartan-3E (v3.4) */ 63*4882a593Smuzhiyun #define XILINX_XC3S100E_SIZE 581344/8 64*4882a593Smuzhiyun #define XILINX_XC3S250E_SIZE 1353728/8 65*4882a593Smuzhiyun #define XILINX_XC3S500E_SIZE 2270208/8 66*4882a593Smuzhiyun #define XILINX_XC3S1200E_SIZE 3841184/8 67*4882a593Smuzhiyun #define XILINX_XC3S1600E_SIZE 5969696/8 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * Spartan-6 : the Spartan-6 family can be programmed 71*4882a593Smuzhiyun * exactly as the Spartan-3 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun #define XILINK_XC6SLX4_SIZE (3713568/8) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Descriptor Macros 76*4882a593Smuzhiyun *********************************************************************/ 77*4882a593Smuzhiyun /* Spartan-III devices */ 78*4882a593Smuzhiyun #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \ 79*4882a593Smuzhiyun { xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \ 80*4882a593Smuzhiyun FPGA_SPARTAN3_OPS } 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define XILINX_XC3S200_DESC(iface, fn_table, cookie) \ 83*4882a593Smuzhiyun { xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \ 84*4882a593Smuzhiyun FPGA_SPARTAN3_OPS } 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define XILINX_XC3S400_DESC(iface, fn_table, cookie) \ 87*4882a593Smuzhiyun { xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \ 88*4882a593Smuzhiyun FPGA_SPARTAN3_OPS } 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \ 91*4882a593Smuzhiyun { xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \ 92*4882a593Smuzhiyun FPGA_SPARTAN3_OPS } 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \ 95*4882a593Smuzhiyun { xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \ 96*4882a593Smuzhiyun FPGA_SPARTAN3_OPS } 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \ 99*4882a593Smuzhiyun { xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \ 100*4882a593Smuzhiyun FPGA_SPARTAN3_OPS } 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \ 103*4882a593Smuzhiyun { xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \ 104*4882a593Smuzhiyun FPGA_SPARTAN3_OPS } 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \ 107*4882a593Smuzhiyun { xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \ 108*4882a593Smuzhiyun FPGA_SPARTAN3_OPS } 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* Spartan-3E devices */ 111*4882a593Smuzhiyun #define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \ 112*4882a593Smuzhiyun { xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \ 113*4882a593Smuzhiyun FPGA_SPARTAN3_OPS } 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \ 116*4882a593Smuzhiyun { xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \ 117*4882a593Smuzhiyun FPGA_SPARTAN3_OPS } 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \ 120*4882a593Smuzhiyun { xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \ 121*4882a593Smuzhiyun FPGA_SPARTAN3_OPS } 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \ 124*4882a593Smuzhiyun { xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \ 125*4882a593Smuzhiyun FPGA_SPARTAN3_OPS } 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \ 128*4882a593Smuzhiyun { xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \ 129*4882a593Smuzhiyun FPGA_SPARTAN3_OPS } 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \ 132*4882a593Smuzhiyun { xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \ 133*4882a593Smuzhiyun FPGA_SPARTAN3_OPS } 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #endif /* _SPARTAN3_H_ */ 136