1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2002 3*4882a593Smuzhiyun * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _SPARTAN2_H_ 9*4882a593Smuzhiyun #define _SPARTAN2_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <xilinx.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Slave Parallel Implementation function table */ 14*4882a593Smuzhiyun typedef struct { 15*4882a593Smuzhiyun xilinx_pre_fn pre; 16*4882a593Smuzhiyun xilinx_pgm_fn pgm; 17*4882a593Smuzhiyun xilinx_init_fn init; 18*4882a593Smuzhiyun xilinx_err_fn err; 19*4882a593Smuzhiyun xilinx_done_fn done; 20*4882a593Smuzhiyun xilinx_clk_fn clk; 21*4882a593Smuzhiyun xilinx_cs_fn cs; 22*4882a593Smuzhiyun xilinx_wr_fn wr; 23*4882a593Smuzhiyun xilinx_rdata_fn rdata; 24*4882a593Smuzhiyun xilinx_wdata_fn wdata; 25*4882a593Smuzhiyun xilinx_busy_fn busy; 26*4882a593Smuzhiyun xilinx_abort_fn abort; 27*4882a593Smuzhiyun xilinx_post_fn post; 28*4882a593Smuzhiyun } xilinx_spartan2_slave_parallel_fns; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* Slave Serial Implementation function table */ 31*4882a593Smuzhiyun typedef struct { 32*4882a593Smuzhiyun xilinx_pre_fn pre; 33*4882a593Smuzhiyun xilinx_pgm_fn pgm; 34*4882a593Smuzhiyun xilinx_clk_fn clk; 35*4882a593Smuzhiyun xilinx_init_fn init; 36*4882a593Smuzhiyun xilinx_done_fn done; 37*4882a593Smuzhiyun xilinx_wr_fn wr; 38*4882a593Smuzhiyun xilinx_post_fn post; 39*4882a593Smuzhiyun } xilinx_spartan2_slave_serial_fns; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #if defined(CONFIG_FPGA_SPARTAN2) 42*4882a593Smuzhiyun extern struct xilinx_fpga_op spartan2_op; 43*4882a593Smuzhiyun # define FPGA_SPARTAN2_OPS &spartan2_op 44*4882a593Smuzhiyun #else 45*4882a593Smuzhiyun # define FPGA_SPARTAN2_OPS NULL 46*4882a593Smuzhiyun #endif 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Device Image Sizes 49*4882a593Smuzhiyun *********************************************************************/ 50*4882a593Smuzhiyun /* Spartan-II (2.5V) */ 51*4882a593Smuzhiyun #define XILINX_XC2S15_SIZE 197728/8 52*4882a593Smuzhiyun #define XILINX_XC2S30_SIZE 336800/8 53*4882a593Smuzhiyun #define XILINX_XC2S50_SIZE 559232/8 54*4882a593Smuzhiyun #define XILINX_XC2S100_SIZE 781248/8 55*4882a593Smuzhiyun #define XILINX_XC2S150_SIZE 1040128/8 56*4882a593Smuzhiyun #define XILINX_XC2S200_SIZE 1335872/8 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Spartan-IIE (1.8V) */ 59*4882a593Smuzhiyun #define XILINX_XC2S50E_SIZE 630048/8 60*4882a593Smuzhiyun #define XILINX_XC2S100E_SIZE 863840/8 61*4882a593Smuzhiyun #define XILINX_XC2S150E_SIZE 1134496/8 62*4882a593Smuzhiyun #define XILINX_XC2S200E_SIZE 1442016/8 63*4882a593Smuzhiyun #define XILINX_XC2S300E_SIZE 1875648/8 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Descriptor Macros 66*4882a593Smuzhiyun *********************************************************************/ 67*4882a593Smuzhiyun /* Spartan-II devices */ 68*4882a593Smuzhiyun #define XILINX_XC2S15_DESC(iface, fn_table, cookie) \ 69*4882a593Smuzhiyun { xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \ 70*4882a593Smuzhiyun FPGA_SPARTAN2_OPS } 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define XILINX_XC2S30_DESC(iface, fn_table, cookie) \ 73*4882a593Smuzhiyun { xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \ 74*4882a593Smuzhiyun FPGA_SPARTAN2_OPS } 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define XILINX_XC2S50_DESC(iface, fn_table, cookie) \ 77*4882a593Smuzhiyun { xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \ 78*4882a593Smuzhiyun FPGA_SPARTAN2_OPS } 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define XILINX_XC2S100_DESC(iface, fn_table, cookie) \ 81*4882a593Smuzhiyun { xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \ 82*4882a593Smuzhiyun FPGA_SPARTAN2_OPS } 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ 85*4882a593Smuzhiyun { xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \ 86*4882a593Smuzhiyun FPGA_SPARTAN2_OPS } 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define XILINX_XC2S200_DESC(iface, fn_table, cookie) \ 89*4882a593Smuzhiyun { xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \ 90*4882a593Smuzhiyun FPGA_SPARTAN2_OPS } 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ 93*4882a593Smuzhiyun { xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \ 94*4882a593Smuzhiyun FPGA_SPARTAN2_OPS } 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \ 97*4882a593Smuzhiyun { xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \ 98*4882a593Smuzhiyun FPGA_SPARTAN2_OPS } 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \ 101*4882a593Smuzhiyun { xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \ 102*4882a593Smuzhiyun FPGA_SPARTAN2_OPS } 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \ 105*4882a593Smuzhiyun { xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \ 106*4882a593Smuzhiyun FPGA_SPARTAN2_OPS } 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \ 109*4882a593Smuzhiyun { xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \ 110*4882a593Smuzhiyun FPGA_SPARTAN2_OPS } 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #endif /* _SPARTAN2_H_ */ 113