1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _SMSC_SIO1007_H_ 8*4882a593Smuzhiyun #define _SMSC_SIO1007_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0 12*4882a593Smuzhiyun * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of 13*4882a593Smuzhiyun * SYSOPT0 and SYSOPT1 determines one of the following addresses. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define SIO1007_IOPORT0 0x002e 16*4882a593Smuzhiyun #define SIO1007_IOPORT1 0x004e 17*4882a593Smuzhiyun #define SIO1007_IOPORT2 0x162e 18*4882a593Smuzhiyun #define SIO1007_IOPORT3 0x164e 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* SIO1007 registers */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define DEV_POWER_CTRL 0x02 23*4882a593Smuzhiyun #define UART1_POWER_ON (1 << 3) 24*4882a593Smuzhiyun #define UART2_POWER_ON (1 << 7) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define UART1_IOBASE 0x24 27*4882a593Smuzhiyun #define UART2_IOBASE 0x25 28*4882a593Smuzhiyun #define UART_IRQ 0x28 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define RTR_IOBASE_HIGH 0x21 31*4882a593Smuzhiyun #define RTR_IOBASE_LOW 0x30 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define GPIO0_DIR 0x31 34*4882a593Smuzhiyun #define GPIO1_DIR 0x35 35*4882a593Smuzhiyun #define GPIO_DIR_INPUT 0 36*4882a593Smuzhiyun #define GPIO_DIR_OUTPUT 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define GPIO0_POL 0x32 39*4882a593Smuzhiyun #define GPIO1_POL 0x36 40*4882a593Smuzhiyun #define GPIO_POL_NO_INVERT 0 41*4882a593Smuzhiyun #define GPIO_POL_INVERT 1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define GPIO0_TYPE 0x33 44*4882a593Smuzhiyun #define GPIO1_TYPE 0x37 45*4882a593Smuzhiyun #define GPIO_TYPE_PUSH_PULL 0 46*4882a593Smuzhiyun #define GPIO_TYPE_OPEN_DRAIN 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define DEV_ACTIVATE 0x3a 49*4882a593Smuzhiyun #define RTR_EN (1 << 1) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Runtime register offset */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define GPIO0_DATA 0xc 54*4882a593Smuzhiyun #define GPIO1_DATA 0xe 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Number of serial ports supported */ 57*4882a593Smuzhiyun #define SIO1007_UART_NUM 2 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Number of gpio pins supported */ 60*4882a593Smuzhiyun #define GPIO_NUM_PER_GROUP 8 61*4882a593Smuzhiyun #define GPIO_GROUP_NUM 2 62*4882a593Smuzhiyun #define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /** 65*4882a593Smuzhiyun * Configure the I/O port address of the specified serial device and 66*4882a593Smuzhiyun * enable the serial device. 67*4882a593Smuzhiyun * 68*4882a593Smuzhiyun * @port: SIO1007 I/O port address 69*4882a593Smuzhiyun * @num: serial device number (0 or 1) 70*4882a593Smuzhiyun * @iobase: processor I/O port address to assign to this serial device 71*4882a593Smuzhiyun * @irq: processor IRQ number to assign to this serial device 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun void sio1007_enable_serial(int port, int num, int iobase, int irq); 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /** 76*4882a593Smuzhiyun * Configure the I/O port address of the runtime register block and 77*4882a593Smuzhiyun * enable the address decoding. 78*4882a593Smuzhiyun * 79*4882a593Smuzhiyun * @port: SIO1007 I/O port address 80*4882a593Smuzhiyun * @iobase: processor I/O port address to assign to the runtime registers 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun void sio1007_enable_runtime(int port, int iobase); 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /** 85*4882a593Smuzhiyun * Configure the direction/polority/type of a specified GPIO pin 86*4882a593Smuzhiyun * 87*4882a593Smuzhiyun * @port: SIO1007 I/O port address 88*4882a593Smuzhiyun * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37) 89*4882a593Smuzhiyun * @dir: GPIO_DIR_INPUT or GPIO_DIR_OUTPUT 90*4882a593Smuzhiyun * @pol: GPIO_POL_NO_INVERT or GPIO_POL_INVERT 91*4882a593Smuzhiyun * @type: GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type); 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /** 96*4882a593Smuzhiyun * Get a GPIO pin value. 97*4882a593Smuzhiyun * This will work whether the GPIO is an input or an output. 98*4882a593Smuzhiyun * 99*4882a593Smuzhiyun * @port: runtime register block I/O port address 100*4882a593Smuzhiyun * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37) 101*4882a593Smuzhiyun * @return: 0 if low, 1 if high, -EINVAL if gpio number is invalid 102*4882a593Smuzhiyun */ 103*4882a593Smuzhiyun int sio1007_gpio_get_value(int port, int gpio); 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /** 106*4882a593Smuzhiyun * Set a GPIO pin value. 107*4882a593Smuzhiyun * This will only work when the GPIO is configured as an output. 108*4882a593Smuzhiyun * 109*4882a593Smuzhiyun * @port: runtime register block I/O port address 110*4882a593Smuzhiyun * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37) 111*4882a593Smuzhiyun * @val: 0 if low, 1 if high 112*4882a593Smuzhiyun */ 113*4882a593Smuzhiyun void sio1007_gpio_set_value(int port, int gpio, int val); 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #endif /* _SMSC_SIO1007_H_ */ 116