1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SJA1000 register layout for basic CAN mode 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _SJA1000_H_ 10*4882a593Smuzhiyun #define _SJA1000_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * SJA1000 register layout in basic can mode 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun struct sja1000_basic_s { 16*4882a593Smuzhiyun u8 cr; 17*4882a593Smuzhiyun u8 cmr; 18*4882a593Smuzhiyun u8 sr; 19*4882a593Smuzhiyun u8 ir; 20*4882a593Smuzhiyun u8 ac; 21*4882a593Smuzhiyun u8 am; 22*4882a593Smuzhiyun u8 btr0; 23*4882a593Smuzhiyun u8 btr1; 24*4882a593Smuzhiyun u8 oc; 25*4882a593Smuzhiyun u8 txb[10]; 26*4882a593Smuzhiyun u8 rxb[10]; 27*4882a593Smuzhiyun u8 unused; 28*4882a593Smuzhiyun u8 cdr; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* control register */ 32*4882a593Smuzhiyun #define CR_RR 0x01 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* output control register */ 35*4882a593Smuzhiyun #define OC_MODE0 0x01 36*4882a593Smuzhiyun #define OC_MODE1 0x02 37*4882a593Smuzhiyun #define OC_POL0 0x04 38*4882a593Smuzhiyun #define OC_TN0 0x08 39*4882a593Smuzhiyun #define OC_TP0 0x10 40*4882a593Smuzhiyun #define OC_POL1 0x20 41*4882a593Smuzhiyun #define OC_TN1 0x40 42*4882a593Smuzhiyun #define OC_TP1 0x80 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #endif 45