1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * SuperH Pin Function Controller Support 3*4882a593Smuzhiyun * Copy from Linux kernel. (include/linux/sh_pfc.h) 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015 Renesas Electronics Corporation 6*4882a593Smuzhiyun * Copyright (c) 2008 Magnus Damm 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 9*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 10*4882a593Smuzhiyun * for more details. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __SH_PFC_H 14*4882a593Smuzhiyun #define __SH_PFC_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun typedef unsigned short pinmux_enum_t; 17*4882a593Smuzhiyun typedef unsigned short pinmux_flag_t; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define PINMUX_TYPE_NONE 0 20*4882a593Smuzhiyun #define PINMUX_TYPE_FUNCTION 1 21*4882a593Smuzhiyun #define PINMUX_TYPE_GPIO 2 22*4882a593Smuzhiyun #define PINMUX_TYPE_OUTPUT 3 23*4882a593Smuzhiyun #define PINMUX_TYPE_INPUT 4 24*4882a593Smuzhiyun #define PINMUX_TYPE_INPUT_PULLUP 5 25*4882a593Smuzhiyun #define PINMUX_TYPE_INPUT_PULLDOWN 6 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define PINMUX_FLAG_TYPE (0x7) 28*4882a593Smuzhiyun #define PINMUX_FLAG_WANT_PULLUP (1 << 3) 29*4882a593Smuzhiyun #define PINMUX_FLAG_WANT_PULLDOWN (1 << 4) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define PINMUX_FLAG_DBIT_SHIFT 5 32*4882a593Smuzhiyun #define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT) 33*4882a593Smuzhiyun #define PINMUX_FLAG_DREG_SHIFT 10 34*4882a593Smuzhiyun #define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct pinmux_gpio { 37*4882a593Smuzhiyun pinmux_enum_t enum_id; 38*4882a593Smuzhiyun pinmux_flag_t flags; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define PINMUX_GPIO(gpio, data_or_mark)[gpio] = { data_or_mark } 42*4882a593Smuzhiyun #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun struct pinmux_cfg_reg { 45*4882a593Smuzhiyun unsigned long reg, reg_width, field_width; 46*4882a593Smuzhiyun unsigned long *cnt; 47*4882a593Smuzhiyun pinmux_enum_t *enum_ids; 48*4882a593Smuzhiyun unsigned long *var_field_width; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define PINMUX_CFG_REG(name, r, r_width, f_width) \ 52*4882a593Smuzhiyun .reg = r, .reg_width = r_width, .field_width = f_width, \ 53*4882a593Smuzhiyun .cnt = (unsigned long [r_width / f_width]) {}, \ 54*4882a593Smuzhiyun .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ 57*4882a593Smuzhiyun .reg = r, .reg_width = r_width, \ 58*4882a593Smuzhiyun .cnt = (unsigned long [r_width]) {}, \ 59*4882a593Smuzhiyun .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ 60*4882a593Smuzhiyun .enum_ids = (pinmux_enum_t []) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct pinmux_data_reg { 63*4882a593Smuzhiyun unsigned long reg, reg_width, reg_shadow; 64*4882a593Smuzhiyun pinmux_enum_t *enum_ids; 65*4882a593Smuzhiyun void *mapped_reg; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define PINMUX_DATA_REG(name, r, r_width) \ 69*4882a593Smuzhiyun .reg = r, .reg_width = r_width, \ 70*4882a593Smuzhiyun .enum_ids = (pinmux_enum_t [r_width]) \ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun struct pinmux_irq { 73*4882a593Smuzhiyun int irq; 74*4882a593Smuzhiyun pinmux_enum_t *enum_ids; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define PINMUX_IRQ(irq_nr, ids...) \ 78*4882a593Smuzhiyun { .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } } \ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun struct pinmux_range { 81*4882a593Smuzhiyun pinmux_enum_t begin; 82*4882a593Smuzhiyun pinmux_enum_t end; 83*4882a593Smuzhiyun pinmux_enum_t force; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun struct pinmux_info { 87*4882a593Smuzhiyun char *name; 88*4882a593Smuzhiyun pinmux_enum_t reserved_id; 89*4882a593Smuzhiyun struct pinmux_range data; 90*4882a593Smuzhiyun struct pinmux_range input; 91*4882a593Smuzhiyun struct pinmux_range input_pd; 92*4882a593Smuzhiyun struct pinmux_range input_pu; 93*4882a593Smuzhiyun struct pinmux_range output; 94*4882a593Smuzhiyun struct pinmux_range mark; 95*4882a593Smuzhiyun struct pinmux_range function; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun unsigned first_gpio, last_gpio; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct pinmux_gpio *gpios; 100*4882a593Smuzhiyun struct pinmux_cfg_reg *cfg_regs; 101*4882a593Smuzhiyun struct pinmux_data_reg *data_regs; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun pinmux_enum_t *gpio_data; 104*4882a593Smuzhiyun unsigned int gpio_data_size; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun struct pinmux_irq *gpio_irq; 107*4882a593Smuzhiyun unsigned int gpio_irq_size; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun struct resource *resource; 110*4882a593Smuzhiyun unsigned int num_resources; 111*4882a593Smuzhiyun unsigned long unlock_reg; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun int register_pinmux(struct pinmux_info *pip); 115*4882a593Smuzhiyun int unregister_pinmux(struct pinmux_info *pip); 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* helper macro for port */ 118*4882a593Smuzhiyun #define PORT_1(fn, pfx, sfx) fn(pfx, sfx) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define PORT_10(fn, pfx, sfx) \ 121*4882a593Smuzhiyun PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ 122*4882a593Smuzhiyun PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ 123*4882a593Smuzhiyun PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ 124*4882a593Smuzhiyun PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ 125*4882a593Smuzhiyun PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define PORT_90(fn, pfx, sfx) \ 128*4882a593Smuzhiyun PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ 129*4882a593Smuzhiyun PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ 130*4882a593Smuzhiyun PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \ 131*4882a593Smuzhiyun PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \ 132*4882a593Smuzhiyun PORT_10(fn, pfx##9, sfx) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define _PORT_ALL(pfx, sfx) pfx##_##sfx 135*4882a593Smuzhiyun #define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) 136*4882a593Smuzhiyun #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) 137*4882a593Smuzhiyun #define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused) 138*4882a593Smuzhiyun #define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) 139*4882a593Smuzhiyun #define GPIO_GFN(str) PINMUX_GPIO(GPIO_GFN_##str, str##_GMARK) 140*4882a593Smuzhiyun #define GPIO_IFN(str) PINMUX_GPIO(GPIO_IFN_##str, str##_IMARK) 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* helper macro for pinmux_enum_t */ 143*4882a593Smuzhiyun #define PORT_DATA_I(nr) \ 144*4882a593Smuzhiyun PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define PORT_DATA_I_PD(nr) \ 147*4882a593Smuzhiyun PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ 148*4882a593Smuzhiyun PORT##nr##_IN, PORT##nr##_IN_PD) 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define PORT_DATA_I_PU(nr) \ 151*4882a593Smuzhiyun PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ 152*4882a593Smuzhiyun PORT##nr##_IN, PORT##nr##_IN_PU) 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define PORT_DATA_I_PU_PD(nr) \ 155*4882a593Smuzhiyun PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ 156*4882a593Smuzhiyun PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define PORT_DATA_O(nr) \ 159*4882a593Smuzhiyun PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT) 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #define PORT_DATA_IO(nr) \ 162*4882a593Smuzhiyun PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ 163*4882a593Smuzhiyun PORT##nr##_IN) 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #define PORT_DATA_IO_PD(nr) \ 166*4882a593Smuzhiyun PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ 167*4882a593Smuzhiyun PORT##nr##_IN, PORT##nr##_IN_PD) 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun #define PORT_DATA_IO_PU(nr) \ 170*4882a593Smuzhiyun PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ 171*4882a593Smuzhiyun PORT##nr##_IN, PORT##nr##_IN_PU) 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun #define PORT_DATA_IO_PU_PD(nr) \ 174*4882a593Smuzhiyun PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ 175*4882a593Smuzhiyun PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* helper macro for top 4 bits in PORTnCR */ 178*4882a593Smuzhiyun #define _PCRH(in, in_pd, in_pu, out) \ 179*4882a593Smuzhiyun 0, (out), (in), 0, \ 180*4882a593Smuzhiyun 0, 0, 0, 0, \ 181*4882a593Smuzhiyun 0, 0, (in_pd), 0, \ 182*4882a593Smuzhiyun 0, 0, (in_pu), 0 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define PORTCR(nr, reg) \ 185*4882a593Smuzhiyun { \ 186*4882a593Smuzhiyun PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ 187*4882a593Smuzhiyun _PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ 188*4882a593Smuzhiyun PORT##nr##_IN_PU, PORT##nr##_OUT), \ 189*4882a593Smuzhiyun PORT##nr##_FN0, PORT##nr##_FN1, \ 190*4882a593Smuzhiyun PORT##nr##_FN2, PORT##nr##_FN3, \ 191*4882a593Smuzhiyun PORT##nr##_FN4, PORT##nr##_FN5, \ 192*4882a593Smuzhiyun PORT##nr##_FN6, PORT##nr##_FN7 } \ 193*4882a593Smuzhiyun } 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun #endif /* __SH_PFC_H */ 196