1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _CRYPTO_HASH_CACHE_H_ 7*4882a593Smuzhiyun #define _CRYPTO_HASH_CACHE_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define HASH_CACHE_SIZE 8192 10*4882a593Smuzhiyun #define CIPHER_CACHE_SIZE 8192 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun typedef int (*crypto_hash_calc)(void *hw_data, const u8 *data, u32 data_len, 13*4882a593Smuzhiyun u8 *started_flag, u8 is_last); 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct crypto_hash_cache { 16*4882a593Smuzhiyun crypto_hash_calc direct_calc; /* hardware hash callback*/ 17*4882a593Smuzhiyun void *user_data; 18*4882a593Smuzhiyun void *cache; /* virt addr for hash src data*/ 19*4882a593Smuzhiyun u32 cache_size; /* data in cached size */ 20*4882a593Smuzhiyun u32 data_align; 21*4882a593Smuzhiyun u32 len_align; 22*4882a593Smuzhiyun u32 left_len; /* left data to calc */ 23*4882a593Smuzhiyun u8 is_started; /* start or restart */ 24*4882a593Smuzhiyun u8 use_cache; /* is use cache or not*/ 25*4882a593Smuzhiyun u8 reserved[2]; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun struct crypto_hash_cache *crypto_hash_cache_alloc(crypto_hash_calc direct_calc, 29*4882a593Smuzhiyun void *user_data, u32 total, 30*4882a593Smuzhiyun u32 data_align, 31*4882a593Smuzhiyun u32 len_align); 32*4882a593Smuzhiyun void crypto_hash_cache_free(struct crypto_hash_cache *hash_cache); 33*4882a593Smuzhiyun int crypto_hash_update_with_cache(struct crypto_hash_cache *hash_cache, 34*4882a593Smuzhiyun const u8 *data, u32 data_len); 35*4882a593Smuzhiyun void crypto_flush_cacheline(ulong addr, ulong size); 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #endif 38