1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _ROCKCHIP_OTP_H_ 7*4882a593Smuzhiyun #define _ROCKCHIP_OTP_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* OTP Register Offsets */ 10*4882a593Smuzhiyun #define OTPC_SBPI_CTRL 0x0020 11*4882a593Smuzhiyun #define OTPC_SBPI_CMD_VALID_PRE 0x0024 12*4882a593Smuzhiyun #define OTPC_SBPI_CS_VALID_PRE 0x0028 13*4882a593Smuzhiyun #define OTPC_SBPI_STATUS 0x002C 14*4882a593Smuzhiyun #define OTPC_USER_CTRL 0x0100 15*4882a593Smuzhiyun #define OTPC_USER_ADDR 0x0104 16*4882a593Smuzhiyun #define OTPC_USER_ENABLE 0x0108 17*4882a593Smuzhiyun #define OTPC_USER_QP 0x0120 18*4882a593Smuzhiyun #define OTPC_USER_Q 0x0124 19*4882a593Smuzhiyun #define OTPC_INT_STATUS 0x0304 20*4882a593Smuzhiyun #define OTPC_SBPI_CMD0_OFFSET 0x1000 21*4882a593Smuzhiyun #define OTPC_SBPI_CMD1_OFFSET 0x1004 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* OTP Register bits and masks */ 24*4882a593Smuzhiyun #define OTPC_USER_ADDR_MASK GENMASK(31, 16) 25*4882a593Smuzhiyun #define OTPC_USE_USER BIT(0) 26*4882a593Smuzhiyun #define OTPC_USE_USER_MASK GENMASK(16, 16) 27*4882a593Smuzhiyun #define OTPC_USER_FSM_ENABLE BIT(0) 28*4882a593Smuzhiyun #define OTPC_USER_FSM_ENABLE_MASK GENMASK(16, 16) 29*4882a593Smuzhiyun #define OTPC_SBPI_DONE BIT(1) 30*4882a593Smuzhiyun #define OTPC_USER_DONE BIT(2) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define SBPI_DAP_ADDR 0x02 33*4882a593Smuzhiyun #define SBPI_DAP_ADDR_SHIFT 8 34*4882a593Smuzhiyun #define SBPI_DAP_ADDR_MASK GENMASK(31, 24) 35*4882a593Smuzhiyun #define SBPI_CMD_VALID_MASK GENMASK(31, 16) 36*4882a593Smuzhiyun #define SBPI_DAP_CMD_WRF 0xC0 37*4882a593Smuzhiyun #define SBPI_DAP_REG_ECC 0x3A 38*4882a593Smuzhiyun #define SBPI_ECC_ENABLE 0x00 39*4882a593Smuzhiyun #define SBPI_ECC_DISABLE 0x09 40*4882a593Smuzhiyun #define SBPI_ENABLE BIT(0) 41*4882a593Smuzhiyun #define SBPI_ENABLE_MASK GENMASK(16, 16) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define OTPC_TIMEOUT 10000 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define OTPC_MODE_CTRL 0x2000 46*4882a593Smuzhiyun #define OTPC_IRQ_ST 0x2008 47*4882a593Smuzhiyun #define OTPC_ACCESS_ADDR 0x200c 48*4882a593Smuzhiyun #define OTPC_RD_DATA 0x2010 49*4882a593Smuzhiyun #define OTPC_REPR_RD_TRANS_NUM 0x2020 50*4882a593Smuzhiyun #define OTPC_DEEP_STANDBY 0x0 51*4882a593Smuzhiyun #define OTPC_STANDBY 0x1 52*4882a593Smuzhiyun #define OTPC_ACTIVE 0x2 53*4882a593Smuzhiyun #define OTPC_READ_ACCESS 0x3 54*4882a593Smuzhiyun #define OTPC_TRANS_NUM 0x1 55*4882a593Smuzhiyun #define OTPC_RDM_IRQ_ST BIT(0) 56*4882a593Smuzhiyun #define OTPC_STB2ACT_IRQ_ST BIT(7) 57*4882a593Smuzhiyun #define OTPC_DP2STB_IRQ_ST BIT(8) 58*4882a593Smuzhiyun #define OTPC_ACT2STB_IRQ_ST BIT(9) 59*4882a593Smuzhiyun #define OTPC_STB2DP_IRQ_ST BIT(10) 60*4882a593Smuzhiyun #define RK3308BS_NBYTES 4 61*4882a593Smuzhiyun #define RK3308BS_MAX_BYTES 0x80 62*4882a593Smuzhiyun #define RK3308BS_NO_SECURE_OFFSET 224 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define RK3568_NBYTES 2 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define RK3588_OTPC_AUTO_CTRL 0x04 67*4882a593Smuzhiyun #define RK3588_OTPC_AUTO_EN 0x08 68*4882a593Smuzhiyun #define RK3588_OTPC_INT_ST 0x84 69*4882a593Smuzhiyun #define RK3588_OTPC_DOUT0 0x20 70*4882a593Smuzhiyun #define RK3588_NO_SECURE_OFFSET 0x300 71*4882a593Smuzhiyun #define RK3588_MAX_BYTES 0x400 72*4882a593Smuzhiyun #define RK3588_NBYTES 4 73*4882a593Smuzhiyun #define RK3588_BURST_NUM 1 74*4882a593Smuzhiyun #define RK3588_BURST_SHIFT 8 75*4882a593Smuzhiyun #define RK3588_ADDR_SHIFT 16 76*4882a593Smuzhiyun #define RK3588_AUTO_EN BIT(0) 77*4882a593Smuzhiyun #define RK3588_RD_DONE BIT(1) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define RV1126_OTP_NVM_CEB 0x00 80*4882a593Smuzhiyun #define RV1126_OTP_NVM_RSTB 0x04 81*4882a593Smuzhiyun #define RV1126_OTP_NVM_ST 0x18 82*4882a593Smuzhiyun #define RV1126_OTP_NVM_RADDR 0x1C 83*4882a593Smuzhiyun #define RV1126_OTP_NVM_RSTART 0x20 84*4882a593Smuzhiyun #define RV1126_OTP_NVM_RDATA 0x24 85*4882a593Smuzhiyun #define RV1126_OTP_NVM_TRWH 0x28 86*4882a593Smuzhiyun #define RV1126_OTP_READ_ST 0x30 87*4882a593Smuzhiyun #define RV1126_OTP_NVM_PRADDR 0x34 88*4882a593Smuzhiyun #define RV1126_OTP_NVM_PRLEN 0x38 89*4882a593Smuzhiyun #define RV1126_OTP_NVM_PRDATA 0x3c 90*4882a593Smuzhiyun #define RV1126_OTP_NVM_FAILTIME 0x40 91*4882a593Smuzhiyun #define RV1126_OTP_NVM_PRSTART 0x44 92*4882a593Smuzhiyun #define RV1126_OTP_NVM_PRSTATE 0x48 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun struct rockchip_otp_platdata { 95*4882a593Smuzhiyun void __iomem *base; 96*4882a593Smuzhiyun unsigned long secure_conf_base; 97*4882a593Smuzhiyun unsigned long otp_mask_base; 98*4882a593Smuzhiyun unsigned long otp_cru_rst_base; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #endif 102