1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * pxa_lcd.h - PXA LCD Controller structures 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2001 5*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _PXA_LCD_H_ 11*4882a593Smuzhiyun #define _PXA_LCD_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * PXA LCD DMA descriptor 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun struct pxafb_dma_descriptor { 17*4882a593Smuzhiyun u_long fdadr; /* Frame descriptor address register */ 18*4882a593Smuzhiyun u_long fsadr; /* Frame source address register */ 19*4882a593Smuzhiyun u_long fidr; /* Frame ID register */ 20*4882a593Smuzhiyun u_long ldcmd; /* Command register */ 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * PXA LCD info 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun struct pxafb_info { 27*4882a593Smuzhiyun /* Misc registers */ 28*4882a593Smuzhiyun u_long reg_lccr3; 29*4882a593Smuzhiyun u_long reg_lccr2; 30*4882a593Smuzhiyun u_long reg_lccr1; 31*4882a593Smuzhiyun u_long reg_lccr0; 32*4882a593Smuzhiyun u_long fdadr0; 33*4882a593Smuzhiyun u_long fdadr1; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* DMA descriptors */ 36*4882a593Smuzhiyun struct pxafb_dma_descriptor *dmadesc_fblow; 37*4882a593Smuzhiyun struct pxafb_dma_descriptor *dmadesc_fbhigh; 38*4882a593Smuzhiyun struct pxafb_dma_descriptor *dmadesc_palette; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun u_long screen; /* physical address of frame buffer */ 41*4882a593Smuzhiyun u_long palette; /* physical address of palette memory */ 42*4882a593Smuzhiyun u_int palette_size; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * LCD controller stucture for PXA CPU 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun typedef struct vidinfo { 49*4882a593Smuzhiyun ushort vl_col; /* Number of columns (i.e. 640) */ 50*4882a593Smuzhiyun ushort vl_row; /* Number of rows (i.e. 480) */ 51*4882a593Smuzhiyun ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ 52*4882a593Smuzhiyun ushort vl_width; /* Width of display area in millimeters */ 53*4882a593Smuzhiyun ushort vl_height; /* Height of display area in millimeters */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* LCD configuration register */ 56*4882a593Smuzhiyun u_char vl_clkp; /* Clock polarity */ 57*4882a593Smuzhiyun u_char vl_oep; /* Output Enable polarity */ 58*4882a593Smuzhiyun u_char vl_hsp; /* Horizontal Sync polarity */ 59*4882a593Smuzhiyun u_char vl_vsp; /* Vertical Sync polarity */ 60*4882a593Smuzhiyun u_char vl_dp; /* Data polarity */ 61*4882a593Smuzhiyun u_char vl_bpix;/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ 62*4882a593Smuzhiyun u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ 63*4882a593Smuzhiyun u_char vl_splt;/* Split display, 0 = single-scan, 1 = dual-scan */ 64*4882a593Smuzhiyun u_char vl_clor; /* Color, 0 = mono, 1 = color */ 65*4882a593Smuzhiyun u_char vl_tft; /* 0 = passive, 1 = TFT */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Horizontal control register. Timing from data sheet */ 68*4882a593Smuzhiyun ushort vl_hpw; /* Horz sync pulse width */ 69*4882a593Smuzhiyun u_char vl_blw; /* Wait before of line */ 70*4882a593Smuzhiyun u_char vl_elw; /* Wait end of line */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Vertical control register. */ 73*4882a593Smuzhiyun u_char vl_vpw; /* Vertical sync pulse width */ 74*4882a593Smuzhiyun u_char vl_bfw; /* Wait before of frame */ 75*4882a593Smuzhiyun u_char vl_efw; /* Wait end of frame */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* PXA LCD controller params */ 78*4882a593Smuzhiyun struct pxafb_info pxa; 79*4882a593Smuzhiyun } vidinfo_t; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif 82