1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2014 3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __POWER_TPS65218_H__ 9*4882a593Smuzhiyun #define __POWER_TPS65218_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/bitops.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* I2C chip address */ 14*4882a593Smuzhiyun #define TPS65218_CHIP_PM 0x24 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Registers */ 17*4882a593Smuzhiyun enum { 18*4882a593Smuzhiyun TPS65218_CHIPID = 0x00, 19*4882a593Smuzhiyun TPS65218_INT1, 20*4882a593Smuzhiyun TPS65218_INT2, 21*4882a593Smuzhiyun TPS65218_INT_MASK1, 22*4882a593Smuzhiyun TPS65218_INT_MASK2, 23*4882a593Smuzhiyun TPS65218_STATUS, 24*4882a593Smuzhiyun TPS65218_CONTROL, 25*4882a593Smuzhiyun TPS65218_FLAG, 26*4882a593Smuzhiyun TPS65218_PASSWORD = 0x10, 27*4882a593Smuzhiyun TPS65218_ENABLE1, 28*4882a593Smuzhiyun TPS65218_ENABLE2, 29*4882a593Smuzhiyun TPS65218_CONFIG1, 30*4882a593Smuzhiyun TPS65218_CONFIG2, 31*4882a593Smuzhiyun TPS65218_CONFIG3, 32*4882a593Smuzhiyun TPS65218_DCDC1, 33*4882a593Smuzhiyun TPS65218_DCDC2, 34*4882a593Smuzhiyun TPS65218_DCDC3, 35*4882a593Smuzhiyun TPS65218_DCDC4, 36*4882a593Smuzhiyun TPS65218_SLEW, 37*4882a593Smuzhiyun TPS65218_LDO1, 38*4882a593Smuzhiyun TPS65218_SEQ1 = 0x20, 39*4882a593Smuzhiyun TPS65218_SEQ2, 40*4882a593Smuzhiyun TPS65218_SEQ3, 41*4882a593Smuzhiyun TPS65218_SEQ4, 42*4882a593Smuzhiyun TPS65218_SEQ5, 43*4882a593Smuzhiyun TPS65218_SEQ6, 44*4882a593Smuzhiyun TPS65218_SEQ7, 45*4882a593Smuzhiyun TPS65218_PMIC_NUM_OF_REGS, 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define TPS65218_PROT_LEVEL_NONE 0x00 49*4882a593Smuzhiyun #define TPS65218_PROT_LEVEL_1 0x01 50*4882a593Smuzhiyun #define TPS65218_PROT_LEVEL_2 0x02 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define TPS65218_PASSWORD_LOCK_FOR_WRITE 0x00 53*4882a593Smuzhiyun #define TPS65218_PASSWORD_UNLOCK 0x7D 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define TPS65218_DCDC_GO 0x80 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define TPS65218_MASK_ALL_BITS 0xFF 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define TPS65218_DCDC_VSEL_MASK 0x3F 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define TPS65218_DCDC_VOLT_SEL_0950MV 0x0a 62*4882a593Smuzhiyun #define TPS65218_DCDC_VOLT_SEL_1100MV 0x19 63*4882a593Smuzhiyun #define TPS65218_DCDC_VOLT_SEL_1200MV 0x23 64*4882a593Smuzhiyun #define TPS65218_DCDC_VOLT_SEL_1260MV 0x29 65*4882a593Smuzhiyun #define TPS65218_DCDC_VOLT_SEL_1330MV 0x30 66*4882a593Smuzhiyun #define TPS65218_DCDC3_VOLT_SEL_1350MV 0x12 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define TPS65218_CC_STAT (BIT(0) | BIT(1)) 69*4882a593Smuzhiyun #define TPS65218_STATE (BIT(2) | BIT(3)) 70*4882a593Smuzhiyun #define TPS65218_PB_STATE BIT(4) 71*4882a593Smuzhiyun #define TPS65218_AC_STATE BIT(5) 72*4882a593Smuzhiyun #define TPS65218_EE BIT(6) 73*4882a593Smuzhiyun #define TPS65218_FSEAL BIT(7) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun int tps65218_reg_read(uchar dest_reg, uchar *dest_val); 76*4882a593Smuzhiyun int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, 77*4882a593Smuzhiyun uchar mask); 78*4882a593Smuzhiyun int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); 79*4882a593Smuzhiyun int tps65218_toggle_fseal(void); 80*4882a593Smuzhiyun int tps65218_lock_fseal(void); 81*4882a593Smuzhiyun int power_tps65218_init(unsigned char bus); 82*4882a593Smuzhiyun #endif /* __POWER_TPS65218_H__ */ 83