1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2011-2013 3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * For more details, please see the TRM at http://www.ti.com/product/tps65217a 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __POWER_TPS65217_H__ 11*4882a593Smuzhiyun #define __POWER_TPS65217_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* I2C chip address */ 14*4882a593Smuzhiyun #define TPS65217_CHIP_PM 0x24 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Registers */ 17*4882a593Smuzhiyun enum { 18*4882a593Smuzhiyun TPS65217_CHIPID = 0x00, 19*4882a593Smuzhiyun TPS65217_POWER_PATH, 20*4882a593Smuzhiyun TPS65217_INTERRUPT, 21*4882a593Smuzhiyun TPS65217_CHGCONFIG0, 22*4882a593Smuzhiyun TPS65217_CHGCONFIG1, 23*4882a593Smuzhiyun TPS65217_CHGCONFIG2, 24*4882a593Smuzhiyun TPS65217_CHGCONFIG3, 25*4882a593Smuzhiyun TPS65217_WLEDCTRL1, 26*4882a593Smuzhiyun TPS65217_WLEDCTRL2, 27*4882a593Smuzhiyun TPS65217_MUXCTRL, 28*4882a593Smuzhiyun TPS65217_STATUS, 29*4882a593Smuzhiyun TPS65217_PASSWORD, 30*4882a593Smuzhiyun TPS65217_PGOOD, 31*4882a593Smuzhiyun TPS65217_DEFPG, 32*4882a593Smuzhiyun TPS65217_DEFDCDC1, 33*4882a593Smuzhiyun TPS65217_DEFDCDC2, 34*4882a593Smuzhiyun TPS65217_DEFDCDC3, 35*4882a593Smuzhiyun TPS65217_DEFSLEW, 36*4882a593Smuzhiyun TPS65217_DEFLDO1, 37*4882a593Smuzhiyun TPS65217_DEFLDO2, 38*4882a593Smuzhiyun TPS65217_DEFLS1, 39*4882a593Smuzhiyun TPS65217_DEFLS2, 40*4882a593Smuzhiyun TPS65217_ENABLE, 41*4882a593Smuzhiyun TPS65217_RESERVED0, /* no 0x17 register available */ 42*4882a593Smuzhiyun TPS65217_DEFUVLO, 43*4882a593Smuzhiyun TPS65217_SEQ1, 44*4882a593Smuzhiyun TPS65217_SEQ2, 45*4882a593Smuzhiyun TPS65217_SEQ3, 46*4882a593Smuzhiyun TPS65217_SEQ4, 47*4882a593Smuzhiyun TPS65217_SEQ5, 48*4882a593Smuzhiyun TPS65217_SEQ6, 49*4882a593Smuzhiyun TPS65217_PMIC_NUM_OF_REGS, 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define TPS65217_PROT_LEVEL_NONE 0x00 53*4882a593Smuzhiyun #define TPS65217_PROT_LEVEL_1 0x01 54*4882a593Smuzhiyun #define TPS65217_PROT_LEVEL_2 0x02 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define TPS65217_PASSWORD_LOCK_FOR_WRITE 0x00 57*4882a593Smuzhiyun #define TPS65217_PASSWORD_UNLOCK 0x7D 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define TPS65217_DCDC_GO 0x80 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define TPS65217_MASK_ALL_BITS 0xFF 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define TPS65217_USB_INPUT_CUR_LIMIT_MASK 0x03 64*4882a593Smuzhiyun #define TPS65217_USB_INPUT_CUR_LIMIT_100MA 0x00 65*4882a593Smuzhiyun #define TPS65217_USB_INPUT_CUR_LIMIT_500MA 0x01 66*4882a593Smuzhiyun #define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02 67*4882a593Smuzhiyun #define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define TPS65217_DCDC_VOLT_SEL_950MV 0x02 70*4882a593Smuzhiyun #define TPS65217_DCDC_VOLT_SEL_1100MV 0x08 71*4882a593Smuzhiyun #define TPS65217_DCDC_VOLT_SEL_1125MV 0x09 72*4882a593Smuzhiyun #define TPS65217_DCDC_VOLT_SEL_1200MV 0x0c 73*4882a593Smuzhiyun #define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F 74*4882a593Smuzhiyun #define TPS65217_DCDC_VOLT_SEL_1325MV 0x11 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define TPS65217_LDO_MASK 0x1F 77*4882a593Smuzhiyun #define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06 78*4882a593Smuzhiyun #define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define TPS65217_PWR_OFF 0x80 81*4882a593Smuzhiyun #define TPS65217_PWR_SRC_USB_BITMASK 0x4 82*4882a593Smuzhiyun #define TPS65217_PWR_SRC_AC_BITMASK 0x8 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun int tps65217_reg_read(uchar src_reg, uchar *src_val); 85*4882a593Smuzhiyun int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, 86*4882a593Smuzhiyun uchar mask); 87*4882a593Smuzhiyun int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); 88*4882a593Smuzhiyun #endif /* __POWER_TPS65217_H__ */ 89