1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2015 Google, Inc 3*4882a593Smuzhiyun * Written by Simon Glass <sjg@chromium.org> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __TPS65090_PMIC_H_ 9*4882a593Smuzhiyun #define __TPS65090_PMIC_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* I2C device address for TPS65090 PMU */ 12*4882a593Smuzhiyun #define TPS65090_I2C_ADDR 0x48 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* TPS65090 register addresses */ 15*4882a593Smuzhiyun enum { 16*4882a593Smuzhiyun REG_IRQ1 = 0, 17*4882a593Smuzhiyun REG_CG_CTRL0 = 4, 18*4882a593Smuzhiyun REG_CG_STATUS1 = 0xa, 19*4882a593Smuzhiyun REG_FET_BASE = 0xe, /* Not a real register, FETs count from here */ 20*4882a593Smuzhiyun REG_FET1_CTRL, 21*4882a593Smuzhiyun REG_FET2_CTRL, 22*4882a593Smuzhiyun REG_FET3_CTRL, 23*4882a593Smuzhiyun REG_FET4_CTRL, 24*4882a593Smuzhiyun REG_FET5_CTRL, 25*4882a593Smuzhiyun REG_FET6_CTRL, 26*4882a593Smuzhiyun REG_FET7_CTRL, 27*4882a593Smuzhiyun TPS65090_NUM_REGS, 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun enum { 31*4882a593Smuzhiyun IRQ1_VBATG = 1 << 3, 32*4882a593Smuzhiyun CG_CTRL0_ENC_MASK = 0x01, 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun MAX_FET_NUM = 7, 35*4882a593Smuzhiyun MAX_CTRL_READ_TRIES = 5, 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* TPS65090 FET_CTRL register values */ 38*4882a593Smuzhiyun FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ 39*4882a593Smuzhiyun FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ 40*4882a593Smuzhiyun FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ 41*4882a593Smuzhiyun FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ 42*4882a593Smuzhiyun FET_CTRL_ENFET = 1 << 0, /* Enable FET */ 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun enum { 46*4882a593Smuzhiyun /* Status register fields */ 47*4882a593Smuzhiyun TPS65090_ST1_OTC = 1 << 0, 48*4882a593Smuzhiyun TPS65090_ST1_OCC = 1 << 1, 49*4882a593Smuzhiyun TPS65090_ST1_STATE_SHIFT = 4, 50*4882a593Smuzhiyun TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT, 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Drivers name */ 54*4882a593Smuzhiyun #define TPS65090_FET_DRIVER "tps65090_fet" 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif /* __TPS65090_PMIC_H_ */ 57