1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015 Samsung Electronics 3*4882a593Smuzhiyun * Przemyslaw Marczak <p.marczak@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _SANDBOX_PMIC_H_ 9*4882a593Smuzhiyun #define _SANDBOX_PMIC_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define SANDBOX_LDO_DRIVER "sandbox_ldo" 12*4882a593Smuzhiyun #define SANDBOX_OF_LDO_PREFIX "ldo" 13*4882a593Smuzhiyun #define SANDBOX_BUCK_DRIVER "sandbox_buck" 14*4882a593Smuzhiyun #define SANDBOX_OF_BUCK_PREFIX "buck" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define SANDBOX_BUCK_COUNT 3 17*4882a593Smuzhiyun #define SANDBOX_LDO_COUNT 2 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * Sandbox PMIC registers: 20*4882a593Smuzhiyun * We have only 12 significant registers, but we alloc 16 for padding. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun enum { 23*4882a593Smuzhiyun SANDBOX_PMIC_REG_BUCK1_UV = 0, 24*4882a593Smuzhiyun SANDBOX_PMIC_REG_BUCK1_UA, 25*4882a593Smuzhiyun SANDBOX_PMIC_REG_BUCK1_OM, 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun SANDBOX_PMIC_REG_BUCK2_UV, 28*4882a593Smuzhiyun SANDBOX_PMIC_REG_BUCK2_UA, 29*4882a593Smuzhiyun SANDBOX_PMIC_REG_BUCK2_OM, 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun SANDBOX_PMIC_REG_LDO_OFFSET, 32*4882a593Smuzhiyun SANDBOX_PMIC_REG_LDO1_UV = SANDBOX_PMIC_REG_LDO_OFFSET, 33*4882a593Smuzhiyun SANDBOX_PMIC_REG_LDO1_UA, 34*4882a593Smuzhiyun SANDBOX_PMIC_REG_LDO1_OM, 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun SANDBOX_PMIC_REG_LDO2_UV, 37*4882a593Smuzhiyun SANDBOX_PMIC_REG_LDO2_UA, 38*4882a593Smuzhiyun SANDBOX_PMIC_REG_LDO2_OM, 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun SANDBOX_PMIC_REG_COUNT = 16, 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Register offset for output: micro Volts, micro Amps, Operation Mode */ 44*4882a593Smuzhiyun enum { 45*4882a593Smuzhiyun OUT_REG_UV = 0, 46*4882a593Smuzhiyun OUT_REG_UA, 47*4882a593Smuzhiyun OUT_REG_OM, 48*4882a593Smuzhiyun OUT_REG_COUNT, 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Buck operation modes */ 52*4882a593Smuzhiyun enum { 53*4882a593Smuzhiyun BUCK_OM_OFF = 0, 54*4882a593Smuzhiyun BUCK_OM_ON, 55*4882a593Smuzhiyun BUCK_OM_PWM, 56*4882a593Smuzhiyun BUCK_OM_COUNT, 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Ldo operation modes */ 60*4882a593Smuzhiyun enum { 61*4882a593Smuzhiyun LDO_OM_OFF = 0, 62*4882a593Smuzhiyun LDO_OM_ON, 63*4882a593Smuzhiyun LDO_OM_SLEEP, 64*4882a593Smuzhiyun LDO_OM_STANDBY, 65*4882a593Smuzhiyun LDO_OM_COUNT, 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* BUCK1 Voltage: min: 0.8V, step: 25mV, max 2.4V */ 69*4882a593Smuzhiyun #define OUT_BUCK1_UV_MIN 800000 70*4882a593Smuzhiyun #define OUT_BUCK1_UV_MAX 2400000 71*4882a593Smuzhiyun #define OUT_BUCK1_UV_STEP 25000 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* BUCK1 Amperage: min: 150mA, step: 25mA, max: 250mA */ 74*4882a593Smuzhiyun #define OUT_BUCK1_UA_MIN 150000 75*4882a593Smuzhiyun #define OUT_BUCK1_UA_MAX 250000 76*4882a593Smuzhiyun #define OUT_BUCK1_UA_STEP 25000 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* BUCK2 Voltage: min: 0.75V, step: 50mV, max 3.95V */ 79*4882a593Smuzhiyun #define OUT_BUCK2_UV_MIN 750000 80*4882a593Smuzhiyun #define OUT_BUCK2_UV_MAX 3950000 81*4882a593Smuzhiyun #define OUT_BUCK2_UV_STEP 50000 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* LDO1 Voltage: min: 0.8V, step: 25mV, max 2.4V */ 84*4882a593Smuzhiyun #define OUT_LDO1_UV_MIN 800000 85*4882a593Smuzhiyun #define OUT_LDO1_UV_MAX 2400000 86*4882a593Smuzhiyun #define OUT_LDO1_UV_STEP 25000 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* LDO1 Amperage: min: 100mA, step: 50mA, max: 200mA */ 89*4882a593Smuzhiyun #define OUT_LDO1_UA_MIN 100000 90*4882a593Smuzhiyun #define OUT_LDO1_UA_MAX 200000 91*4882a593Smuzhiyun #define OUT_LDO1_UA_STEP 50000 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* LDO2 Voltage: min: 0.75V, step: 50mV, max 3.95V */ 94*4882a593Smuzhiyun #define OUT_LDO2_UV_MIN 750000 95*4882a593Smuzhiyun #define OUT_LDO2_UV_MAX 3950000 96*4882a593Smuzhiyun #define OUT_LDO2_UV_STEP 50000 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* register <-> value conversion */ 99*4882a593Smuzhiyun #define REG2VAL(min, step, reg) ((min) + ((step) * (reg))) 100*4882a593Smuzhiyun #define VAL2REG(min, step, val) (((val) - (min)) / (step)) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* Operation mode id -> register value conversion */ 103*4882a593Smuzhiyun #define OM2REG(x) (x) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* Test data for: test/dm/power.c */ 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* BUCK names */ 108*4882a593Smuzhiyun #define SANDBOX_BUCK1_DEVNAME "buck1" 109*4882a593Smuzhiyun #define SANDBOX_BUCK1_PLATNAME "SUPPLY_1.2V" 110*4882a593Smuzhiyun #define SANDBOX_BUCK2_DEVNAME "buck2" 111*4882a593Smuzhiyun #define SANDBOX_BUCK2_PLATNAME "SUPPLY_3.3V" 112*4882a593Smuzhiyun /* BUCK3: for testing fallback regulator prefix matching during bind */ 113*4882a593Smuzhiyun #define SANDBOX_BUCK3_DEVNAME "no_match_by_nodename" 114*4882a593Smuzhiyun #define SANDBOX_BUCK3_PLATNAME "buck_SUPPLY_1.5V" 115*4882a593Smuzhiyun /* LDO names */ 116*4882a593Smuzhiyun #define SANDBOX_LDO1_DEVNAME "ldo1" 117*4882a593Smuzhiyun #define SANDBOX_LDO1_PLATNAME "VDD_EMMC_1.8V" 118*4882a593Smuzhiyun #define SANDBOX_LDO2_DEVNAME "ldo2" 119*4882a593Smuzhiyun #define SANDBOX_LDO2_PLATNAME "VDD_LCD_3.3V" 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* 122*4882a593Smuzhiyun * Expected regulators setup after call of: 123*4882a593Smuzhiyun * - regulator_autoset_by_name() 124*4882a593Smuzhiyun * - regulator_list_autoset() 125*4882a593Smuzhiyun */ 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* BUCK1: for testing regulator_autoset_by_name() */ 128*4882a593Smuzhiyun #define SANDBOX_BUCK1_AUTOSET_EXPECTED_UV 1200000 129*4882a593Smuzhiyun #define SANDBOX_BUCK1_AUTOSET_EXPECTED_UA 200000 130*4882a593Smuzhiyun #define SANDBOX_BUCK1_AUTOSET_EXPECTED_ENABLE true 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* BUCK2: for testing sandbox ADC's supply */ 133*4882a593Smuzhiyun #define SANDBOX_BUCK2_INITIAL_EXPECTED_UV 3000000 134*4882a593Smuzhiyun #define SANDBOX_BUCK2_SET_UV 3300000 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* LDO1/2 for testing regulator_list_autoset() */ 137*4882a593Smuzhiyun #define SANDBOX_LDO1_AUTOSET_EXPECTED_UV 1800000 138*4882a593Smuzhiyun #define SANDBOX_LDO1_AUTOSET_EXPECTED_UA 100000 139*4882a593Smuzhiyun #define SANDBOX_LDO1_AUTOSET_EXPECTED_ENABLE true 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define SANDBOX_LDO2_AUTOSET_EXPECTED_UV 3000000 142*4882a593Smuzhiyun #define SANDBOX_LDO2_AUTOSET_EXPECTED_UA -ENOSYS 143*4882a593Smuzhiyun #define SANDBOX_LDO2_AUTOSET_EXPECTED_ENABLE false 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #endif 146