1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2015 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __S5M8767_H_ 8*4882a593Smuzhiyun #define __S5M8767_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun enum s5m8767_regnum { 11*4882a593Smuzhiyun S5M8767_BUCK1 = 0, 12*4882a593Smuzhiyun S5M8767_BUCK2, 13*4882a593Smuzhiyun S5M8767_BUCK3, 14*4882a593Smuzhiyun S5M8767_BUCK4, 15*4882a593Smuzhiyun S5M8767_BUCK5, 16*4882a593Smuzhiyun S5M8767_BUCK6, 17*4882a593Smuzhiyun S5M8767_BUCK7, 18*4882a593Smuzhiyun S5M8767_BUCK8, 19*4882a593Smuzhiyun S5M8767_BUCK9, 20*4882a593Smuzhiyun S5M8767_LDO1, 21*4882a593Smuzhiyun S5M8767_LDO2, 22*4882a593Smuzhiyun S5M8767_LDO3, 23*4882a593Smuzhiyun S5M8767_LDO4, 24*4882a593Smuzhiyun S5M8767_LDO5, 25*4882a593Smuzhiyun S5M8767_LDO6, 26*4882a593Smuzhiyun S5M8767_LDO7, 27*4882a593Smuzhiyun S5M8767_LDO8, 28*4882a593Smuzhiyun S5M8767_LDO9, 29*4882a593Smuzhiyun S5M8767_LDO10, 30*4882a593Smuzhiyun S5M8767_LDO11, 31*4882a593Smuzhiyun S5M8767_LDO12, 32*4882a593Smuzhiyun S5M8767_LDO13, 33*4882a593Smuzhiyun S5M8767_LDO14, 34*4882a593Smuzhiyun S5M8767_LDO15, 35*4882a593Smuzhiyun S5M8767_LDO16, 36*4882a593Smuzhiyun S5M8767_LDO17, 37*4882a593Smuzhiyun S5M8767_LDO18, 38*4882a593Smuzhiyun S5M8767_LDO19, 39*4882a593Smuzhiyun S5M8767_LDO20, 40*4882a593Smuzhiyun S5M8767_LDO21, 41*4882a593Smuzhiyun S5M8767_LDO22, 42*4882a593Smuzhiyun S5M8767_LDO23, 43*4882a593Smuzhiyun S5M8767_LDO24, 44*4882a593Smuzhiyun S5M8767_LDO25, 45*4882a593Smuzhiyun S5M8767_LDO26, 46*4882a593Smuzhiyun S5M8767_LDO27, 47*4882a593Smuzhiyun S5M8767_LDO28, 48*4882a593Smuzhiyun S5M8767_EN32KHZ_CP, 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun S5M8767_NUM_OF_REGS, 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct sec_voltage_desc { 54*4882a593Smuzhiyun int max; 55*4882a593Smuzhiyun int min; 56*4882a593Smuzhiyun int step; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /** 60*4882a593Smuzhiyun * struct s5m8767_para - s5m8767 register parameters 61*4882a593Smuzhiyun * @param vol_addr i2c address of the given buck/ldo register 62*4882a593Smuzhiyun * @param vol_bitpos bit position to be set or clear within register 63*4882a593Smuzhiyun * @param vol_bitmask bit mask value 64*4882a593Smuzhiyun * @param reg_enaddr control register address, which enable the given 65*4882a593Smuzhiyun * given buck/ldo. 66*4882a593Smuzhiyun * @param reg_enbiton value to be written to buck/ldo to make it ON 67*4882a593Smuzhiyun * @param vol Voltage information 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun struct s5m8767_para { 70*4882a593Smuzhiyun enum s5m8767_regnum regnum; 71*4882a593Smuzhiyun u8 vol_addr; 72*4882a593Smuzhiyun u8 vol_bitpos; 73*4882a593Smuzhiyun u8 vol_bitmask; 74*4882a593Smuzhiyun u8 reg_enaddr; 75*4882a593Smuzhiyun u8 reg_enbiton; 76*4882a593Smuzhiyun const struct sec_voltage_desc *vol; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* Drivers name */ 80*4882a593Smuzhiyun #define S5M8767_LDO_DRIVER "s5m8767_ldo" 81*4882a593Smuzhiyun #define S5M8767_BUCK_DRIVER "s5m8767_buck" 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun int s5m8767_enable_32khz_cp(struct udevice *dev); 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #endif /* __S5M8767_PMIC_H_ */ 86