1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2014 Gateworks Corporation 3*4882a593Smuzhiyun * Tim Harvey <tharvey@gateworks.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __PFUZE100_PMIC_H_ 9*4882a593Smuzhiyun #define __PFUZE100_PMIC_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Device ID */ 12*4882a593Smuzhiyun enum {PFUZE100 = 0x10, PFUZE200 = 0x11, PFUZE3000 = 0x30}; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define PFUZE100_REGULATOR_DRIVER "pfuze100_regulator" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* PFUZE100 registers */ 17*4882a593Smuzhiyun enum { 18*4882a593Smuzhiyun PFUZE100_DEVICEID = 0x00, 19*4882a593Smuzhiyun PFUZE100_REVID = 0x03, 20*4882a593Smuzhiyun PFUZE100_FABID = 0x04, 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun PFUZE100_SW1ABVOL = 0x20, 23*4882a593Smuzhiyun PFUZE100_SW1ABSTBY = 0x21, 24*4882a593Smuzhiyun PFUZE100_SW1ABOFF = 0x22, 25*4882a593Smuzhiyun PFUZE100_SW1ABMODE = 0x23, 26*4882a593Smuzhiyun PFUZE100_SW1ABCONF = 0x24, 27*4882a593Smuzhiyun PFUZE100_SW1CVOL = 0x2e, 28*4882a593Smuzhiyun PFUZE100_SW1CSTBY = 0x2f, 29*4882a593Smuzhiyun PFUZE100_SW1COFF = 0x30, 30*4882a593Smuzhiyun PFUZE100_SW1CMODE = 0x31, 31*4882a593Smuzhiyun PFUZE100_SW1CCONF = 0x32, 32*4882a593Smuzhiyun PFUZE100_SW2VOL = 0x35, 33*4882a593Smuzhiyun PFUZE100_SW2STBY = 0x36, 34*4882a593Smuzhiyun PFUZE100_SW2OFF = 0x37, 35*4882a593Smuzhiyun PFUZE100_SW2MODE = 0x38, 36*4882a593Smuzhiyun PFUZE100_SW2CONF = 0x39, 37*4882a593Smuzhiyun PFUZE100_SW3AVOL = 0x3c, 38*4882a593Smuzhiyun PFUZE100_SW3ASTBY = 0x3D, 39*4882a593Smuzhiyun PFUZE100_SW3AOFF = 0x3E, 40*4882a593Smuzhiyun PFUZE100_SW3AMODE = 0x3F, 41*4882a593Smuzhiyun PFUZE100_SW3ACONF = 0x40, 42*4882a593Smuzhiyun PFUZE100_SW3BVOL = 0x43, 43*4882a593Smuzhiyun PFUZE100_SW3BSTBY = 0x44, 44*4882a593Smuzhiyun PFUZE100_SW3BOFF = 0x45, 45*4882a593Smuzhiyun PFUZE100_SW3BMODE = 0x46, 46*4882a593Smuzhiyun PFUZE100_SW3BCONF = 0x47, 47*4882a593Smuzhiyun PFUZE100_SW4VOL = 0x4a, 48*4882a593Smuzhiyun PFUZE100_SW4STBY = 0x4b, 49*4882a593Smuzhiyun PFUZE100_SW4OFF = 0x4c, 50*4882a593Smuzhiyun PFUZE100_SW4MODE = 0x4d, 51*4882a593Smuzhiyun PFUZE100_SW4CONF = 0x4e, 52*4882a593Smuzhiyun PFUZE100_SWBSTCON1 = 0x66, 53*4882a593Smuzhiyun PFUZE100_VREFDDRCON = 0x6a, 54*4882a593Smuzhiyun PFUZE100_VSNVSVOL = 0x6b, 55*4882a593Smuzhiyun PFUZE100_VGEN1VOL = 0x6c, 56*4882a593Smuzhiyun PFUZE100_VGEN2VOL = 0x6d, 57*4882a593Smuzhiyun PFUZE100_VGEN3VOL = 0x6e, 58*4882a593Smuzhiyun PFUZE100_VGEN4VOL = 0x6f, 59*4882a593Smuzhiyun PFUZE100_VGEN5VOL = 0x70, 60*4882a593Smuzhiyun PFUZE100_VGEN6VOL = 0x71, 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun PFUZE100_NUM_OF_REGS = 0x7f, 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Registor offset based on VOLT register */ 66*4882a593Smuzhiyun #define PFUZE100_VOL_OFFSET 0 67*4882a593Smuzhiyun #define PFUZE100_STBY_OFFSET 1 68*4882a593Smuzhiyun #define PFUZE100_OFF_OFFSET 2 69*4882a593Smuzhiyun #define PFUZE100_MODE_OFFSET 3 70*4882a593Smuzhiyun #define PFUZE100_CONF_OFFSET 4 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * Buck Regulators 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define PFUZE100_SW1ABC_SETP(x) ((x - 3000) / 250) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* SW1A/B/C Output Voltage Configuration */ 79*4882a593Smuzhiyun #define SW1x_0_300V 0 80*4882a593Smuzhiyun #define SW1x_0_325V 1 81*4882a593Smuzhiyun #define SW1x_0_350V 2 82*4882a593Smuzhiyun #define SW1x_0_375V 3 83*4882a593Smuzhiyun #define SW1x_0_400V 4 84*4882a593Smuzhiyun #define SW1x_0_425V 5 85*4882a593Smuzhiyun #define SW1x_0_450V 6 86*4882a593Smuzhiyun #define SW1x_0_475V 7 87*4882a593Smuzhiyun #define SW1x_0_500V 8 88*4882a593Smuzhiyun #define SW1x_0_525V 9 89*4882a593Smuzhiyun #define SW1x_0_550V 10 90*4882a593Smuzhiyun #define SW1x_0_575V 11 91*4882a593Smuzhiyun #define SW1x_0_600V 12 92*4882a593Smuzhiyun #define SW1x_0_625V 13 93*4882a593Smuzhiyun #define SW1x_0_650V 14 94*4882a593Smuzhiyun #define SW1x_0_675V 15 95*4882a593Smuzhiyun #define SW1x_0_700V 16 96*4882a593Smuzhiyun #define SW1x_0_725V 17 97*4882a593Smuzhiyun #define SW1x_0_750V 18 98*4882a593Smuzhiyun #define SW1x_0_775V 19 99*4882a593Smuzhiyun #define SW1x_0_800V 20 100*4882a593Smuzhiyun #define SW1x_0_825V 21 101*4882a593Smuzhiyun #define SW1x_0_850V 22 102*4882a593Smuzhiyun #define SW1x_0_875V 23 103*4882a593Smuzhiyun #define SW1x_0_900V 24 104*4882a593Smuzhiyun #define SW1x_0_925V 25 105*4882a593Smuzhiyun #define SW1x_0_950V 26 106*4882a593Smuzhiyun #define SW1x_0_975V 27 107*4882a593Smuzhiyun #define SW1x_1_000V 28 108*4882a593Smuzhiyun #define SW1x_1_025V 29 109*4882a593Smuzhiyun #define SW1x_1_050V 30 110*4882a593Smuzhiyun #define SW1x_1_075V 31 111*4882a593Smuzhiyun #define SW1x_1_100V 32 112*4882a593Smuzhiyun #define SW1x_1_125V 33 113*4882a593Smuzhiyun #define SW1x_1_150V 34 114*4882a593Smuzhiyun #define SW1x_1_175V 35 115*4882a593Smuzhiyun #define SW1x_1_200V 36 116*4882a593Smuzhiyun #define SW1x_1_225V 37 117*4882a593Smuzhiyun #define SW1x_1_250V 38 118*4882a593Smuzhiyun #define SW1x_1_275V 39 119*4882a593Smuzhiyun #define SW1x_1_300V 40 120*4882a593Smuzhiyun #define SW1x_1_325V 41 121*4882a593Smuzhiyun #define SW1x_1_350V 42 122*4882a593Smuzhiyun #define SW1x_1_375V 43 123*4882a593Smuzhiyun #define SW1x_1_400V 44 124*4882a593Smuzhiyun #define SW1x_1_425V 45 125*4882a593Smuzhiyun #define SW1x_1_450V 46 126*4882a593Smuzhiyun #define SW1x_1_475V 47 127*4882a593Smuzhiyun #define SW1x_1_500V 48 128*4882a593Smuzhiyun #define SW1x_1_525V 49 129*4882a593Smuzhiyun #define SW1x_1_550V 50 130*4882a593Smuzhiyun #define SW1x_1_575V 51 131*4882a593Smuzhiyun #define SW1x_1_600V 52 132*4882a593Smuzhiyun #define SW1x_1_625V 53 133*4882a593Smuzhiyun #define SW1x_1_650V 54 134*4882a593Smuzhiyun #define SW1x_1_675V 55 135*4882a593Smuzhiyun #define SW1x_1_700V 56 136*4882a593Smuzhiyun #define SW1x_1_725V 57 137*4882a593Smuzhiyun #define SW1x_1_750V 58 138*4882a593Smuzhiyun #define SW1x_1_775V 59 139*4882a593Smuzhiyun #define SW1x_1_800V 60 140*4882a593Smuzhiyun #define SW1x_1_825V 61 141*4882a593Smuzhiyun #define SW1x_1_850V 62 142*4882a593Smuzhiyun #define SW1x_1_875V 63 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define SW1x_NORMAL_MASK 0x3f 145*4882a593Smuzhiyun #define SW1x_STBY_MASK 0x3f 146*4882a593Smuzhiyun #define SW1x_OFF_MASK 0x3f 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define SW_MODE_MASK 0xf 149*4882a593Smuzhiyun #define SW_MODE_SHIFT 0 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define SW1xCONF_DVSSPEED_MASK 0xc0 152*4882a593Smuzhiyun #define SW1xCONF_DVSSPEED_2US 0x00 153*4882a593Smuzhiyun #define SW1xCONF_DVSSPEED_4US 0x40 154*4882a593Smuzhiyun #define SW1xCONF_DVSSPEED_8US 0x80 155*4882a593Smuzhiyun #define SW1xCONF_DVSSPEED_16US 0xc0 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /* 158*4882a593Smuzhiyun * LDO Configuration 159*4882a593Smuzhiyun */ 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* VGEN1/2 Voltage Configuration */ 162*4882a593Smuzhiyun #define LDOA_0_80V 0 163*4882a593Smuzhiyun #define LDOA_0_85V 1 164*4882a593Smuzhiyun #define LDOA_0_90V 2 165*4882a593Smuzhiyun #define LDOA_0_95V 3 166*4882a593Smuzhiyun #define LDOA_1_00V 4 167*4882a593Smuzhiyun #define LDOA_1_05V 5 168*4882a593Smuzhiyun #define LDOA_1_10V 6 169*4882a593Smuzhiyun #define LDOA_1_15V 7 170*4882a593Smuzhiyun #define LDOA_1_20V 8 171*4882a593Smuzhiyun #define LDOA_1_25V 9 172*4882a593Smuzhiyun #define LDOA_1_30V 10 173*4882a593Smuzhiyun #define LDOA_1_35V 11 174*4882a593Smuzhiyun #define LDOA_1_40V 12 175*4882a593Smuzhiyun #define LDOA_1_45V 13 176*4882a593Smuzhiyun #define LDOA_1_50V 14 177*4882a593Smuzhiyun #define LDOA_1_55V 15 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* VGEN3/4/5/6 Voltage Configuration */ 180*4882a593Smuzhiyun #define LDOB_1_80V 0 181*4882a593Smuzhiyun #define LDOB_1_90V 1 182*4882a593Smuzhiyun #define LDOB_2_00V 2 183*4882a593Smuzhiyun #define LDOB_2_10V 3 184*4882a593Smuzhiyun #define LDOB_2_20V 4 185*4882a593Smuzhiyun #define LDOB_2_30V 5 186*4882a593Smuzhiyun #define LDOB_2_40V 6 187*4882a593Smuzhiyun #define LDOB_2_50V 7 188*4882a593Smuzhiyun #define LDOB_2_60V 8 189*4882a593Smuzhiyun #define LDOB_2_70V 9 190*4882a593Smuzhiyun #define LDOB_2_80V 10 191*4882a593Smuzhiyun #define LDOB_2_90V 11 192*4882a593Smuzhiyun #define LDOB_3_00V 12 193*4882a593Smuzhiyun #define LDOB_3_10V 13 194*4882a593Smuzhiyun #define LDOB_3_20V 14 195*4882a593Smuzhiyun #define LDOB_3_30V 15 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun #define LDO_VOL_MASK 0xf 198*4882a593Smuzhiyun #define LDO_EN (1 << 4) 199*4882a593Smuzhiyun #define LDO_MODE_SHIFT 4 200*4882a593Smuzhiyun #define LDO_MODE_MASK (1 << 4) 201*4882a593Smuzhiyun #define LDO_MODE_OFF 0 202*4882a593Smuzhiyun #define LDO_MODE_ON 1 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun #define VREFDDRCON_EN (1 << 4) 205*4882a593Smuzhiyun /* 206*4882a593Smuzhiyun * Boost Regulator 207*4882a593Smuzhiyun */ 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun /* SWBST Output Voltage */ 210*4882a593Smuzhiyun #define SWBST_5_00V 0 211*4882a593Smuzhiyun #define SWBST_5_05V 1 212*4882a593Smuzhiyun #define SWBST_5_10V 2 213*4882a593Smuzhiyun #define SWBST_5_15V 3 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun #define SWBST_VOL_MASK 0x3 216*4882a593Smuzhiyun #define SWBST_MODE_MASK 0xC 217*4882a593Smuzhiyun #define SWBST_MODE_SHIFT 0x2 218*4882a593Smuzhiyun #define SWBST_MODE_OFF 0 219*4882a593Smuzhiyun #define SWBST_MODE_PFM 1 220*4882a593Smuzhiyun #define SWBST_MODE_AUTO 2 221*4882a593Smuzhiyun #define SWBST_MODE_APS 3 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun /* 224*4882a593Smuzhiyun * Regulator Mode Control 225*4882a593Smuzhiyun * 226*4882a593Smuzhiyun * OFF: The regulator is switched off and the output voltage is discharged. 227*4882a593Smuzhiyun * PFM: In this mode, the regulator is always in PFM mode, which is useful 228*4882a593Smuzhiyun * at light loads for optimized efficiency. 229*4882a593Smuzhiyun * PWM: In this mode, the regulator is always in PWM mode operation 230*4882a593Smuzhiyun * regardless of load conditions. 231*4882a593Smuzhiyun * APS: In this mode, the regulator moves automatically between pulse 232*4882a593Smuzhiyun * skipping mode and PWM mode depending on load conditions. 233*4882a593Smuzhiyun * 234*4882a593Smuzhiyun * SWxMODE[3:0] 235*4882a593Smuzhiyun * Normal Mode | Standby Mode | value 236*4882a593Smuzhiyun * OFF OFF 0x0 237*4882a593Smuzhiyun * PWM OFF 0x1 238*4882a593Smuzhiyun * PFM OFF 0x3 239*4882a593Smuzhiyun * APS OFF 0x4 240*4882a593Smuzhiyun * PWM PWM 0x5 241*4882a593Smuzhiyun * PWM APS 0x6 242*4882a593Smuzhiyun * APS APS 0x8 243*4882a593Smuzhiyun * APS PFM 0xc 244*4882a593Smuzhiyun * PWM PFM 0xd 245*4882a593Smuzhiyun */ 246*4882a593Smuzhiyun #define OFF_OFF 0x0 247*4882a593Smuzhiyun #define PWM_OFF 0x1 248*4882a593Smuzhiyun #define PFM_OFF 0x3 249*4882a593Smuzhiyun #define APS_OFF 0x4 250*4882a593Smuzhiyun #define PWM_PWM 0x5 251*4882a593Smuzhiyun #define PWM_APS 0x6 252*4882a593Smuzhiyun #define APS_APS 0x8 253*4882a593Smuzhiyun #define APS_PFM 0xc 254*4882a593Smuzhiyun #define PWM_PFM 0xd 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun #define SWITCH_SIZE 0x7 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun int power_pfuze100_init(unsigned char bus); 259*4882a593Smuzhiyun #endif 260