xref: /OK3568_Linux_fs/u-boot/include/power/mc34vr500_pmic.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2016 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun  * Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef __MC34VR500_H_
9*4882a593Smuzhiyun #define __MC34VR500_H_
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <power/pmic.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define MC34VR500_I2C_ADDR	0x08
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun /* Drivers name */
16*4882a593Smuzhiyun #define MC34VR500_REGULATOR_DRIVER	"mc34vr500_regulator"
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /* Register map */
19*4882a593Smuzhiyun enum {
20*4882a593Smuzhiyun 	MC34VR500_DEVICEID		= 0x00,
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun 	MC34VR500_SILICONREVID		= 0x03,
23*4882a593Smuzhiyun 	MC34VR500_FABID,
24*4882a593Smuzhiyun 	MC34VR500_INTSTAT0,
25*4882a593Smuzhiyun 	MC34VR500_INTMASK0,
26*4882a593Smuzhiyun 	MC34VR500_INTSENSE0,
27*4882a593Smuzhiyun 	MC34VR500_INTSTAT1,
28*4882a593Smuzhiyun 	MC34VR500_INTMASK1,
29*4882a593Smuzhiyun 	MC34VR500_INTSENSE1,
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 	MC34VR500_INTSTAT4		= 0x11,
32*4882a593Smuzhiyun 	MC34VR500_INTMASK4,
33*4882a593Smuzhiyun 	MC34VR500_INTSENSE4,
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 	MC34VR500_PWRCTL		= 0x1B,
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	MC34VR500_SW1VOLT		= 0x2E,
38*4882a593Smuzhiyun 	MC34VR500_SW1STBY,
39*4882a593Smuzhiyun 	MC34VR500_SW1OFF,
40*4882a593Smuzhiyun 	MC34VR500_SW1MODE,
41*4882a593Smuzhiyun 	MC34VR500_SW1CONF,
42*4882a593Smuzhiyun 	MC34VR500_SW2VOLT,
43*4882a593Smuzhiyun 	MC34VR500_SW2STBY,
44*4882a593Smuzhiyun 	MC34VR500_SW2OFF,
45*4882a593Smuzhiyun 	MC34VR500_SW2MODE,
46*4882a593Smuzhiyun 	MC34VR500_SW2CONF,
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	MC34VR500_SW3VOLT		= 0x3C,
49*4882a593Smuzhiyun 	MC34VR500_SW3STBY,
50*4882a593Smuzhiyun 	MC34VR500_SW3OFF,
51*4882a593Smuzhiyun 	MC34VR500_SW3MODE,
52*4882a593Smuzhiyun 	MC34VR500_SW3CONF,
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	MC34VR500_SW4VOLT		= 0x4A,
55*4882a593Smuzhiyun 	MC34VR500_SW4STBY,
56*4882a593Smuzhiyun 	MC34VR500_SW4OFF,
57*4882a593Smuzhiyun 	MC34VR500_SW4MODE,
58*4882a593Smuzhiyun 	MC34VR500_SW4CONF,
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	MC34VR500_REFOUTCRTRL		= 0x6A,
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	MC34VR500_LDO1CTL		= 0x6D,
63*4882a593Smuzhiyun 	MC34VR500_LDO2CTL,
64*4882a593Smuzhiyun 	MC34VR500_LDO3CTL,
65*4882a593Smuzhiyun 	MC34VR500_LDO4CTL,
66*4882a593Smuzhiyun 	MC34VR500_LDO5CTL,
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	MC34VR500_PAGE_REGISTER		= 0x7F,
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	/* Internal RAM */
71*4882a593Smuzhiyun 	MC34VR500_SW1_VOLT		= 0xA8,
72*4882a593Smuzhiyun 	MC34VR500_SW1_SEQ,
73*4882a593Smuzhiyun 	MC34VR500_SW1_CONFIG,
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	MC34VR500_SW2_VOLT		= 0xAC,
76*4882a593Smuzhiyun 	MC34VR500_SW2_SEQ,
77*4882a593Smuzhiyun 	MC34VR500_SW2_CONFIG,
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	MC34VR500_SW3_VOLT		= 0xB0,
80*4882a593Smuzhiyun 	MC34VR500_SW3_SEQ,
81*4882a593Smuzhiyun 	MC34VR500_SW3_CONFIG,
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	MC34VR500_SW4_VOLT		= 0xB8,
84*4882a593Smuzhiyun 	MC34VR500_SW4_SEQ,
85*4882a593Smuzhiyun 	MC34VR500_SW4_CONFIG,
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	MC34VR500_REFOUT_SEQ		= 0xC4,
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	MC34VR500_LDO1_VOLT		= 0xCC,
90*4882a593Smuzhiyun 	MC34VR500_LDO1_SEQ,
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	MC34VR500_LDO2_VOLT		= 0xD0,
93*4882a593Smuzhiyun 	MC34VR500_LDO2_SEQ,
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	MC34VR500_LDO3_VOLT		= 0xD4,
96*4882a593Smuzhiyun 	MC34VR500_LDO3_SEQ,
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	MC34VR500_LDO4_VOLT		= 0xD8,
99*4882a593Smuzhiyun 	MC34VR500_LDO4_SEQ,
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	MC34VR500_LDO5_VOLT		= 0xDC,
102*4882a593Smuzhiyun 	MC34VR500_LDO5_SEQ,
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	MC34VR500_PU_CONFIG1		= 0xE0,
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	MC34VR500_TBB_POR		= 0xE4,
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	MC34VR500_PWRGD_EN		= 0xE8,
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	MC34VR500_NUM_OF_REGS,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun /* Registor offset based on SWxVOLT register */
114*4882a593Smuzhiyun #define MC34VR500_VOLT_OFFSET	0
115*4882a593Smuzhiyun #define MC34VR500_STBY_OFFSET	1
116*4882a593Smuzhiyun #define MC34VR500_OFF_OFFSET	2
117*4882a593Smuzhiyun #define MC34VR500_MODE_OFFSET	3
118*4882a593Smuzhiyun #define MC34VR500_CONF_OFFSET	4
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun #define SW_MODE_MASK	0xf
121*4882a593Smuzhiyun #define SW_MODE_SHIFT	0
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun #define LDO_VOL_MASK	0xf
124*4882a593Smuzhiyun #define LDO_EN		(1 << 4)
125*4882a593Smuzhiyun #define LDO_MODE_SHIFT	4
126*4882a593Smuzhiyun #define LDO_MODE_MASK	(1 << 4)
127*4882a593Smuzhiyun #define LDO_MODE_OFF	0
128*4882a593Smuzhiyun #define LDO_MODE_ON	1
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun #define REFOUTEN	(1 << 4)
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun /*
133*4882a593Smuzhiyun  * Regulator Mode Control
134*4882a593Smuzhiyun  *
135*4882a593Smuzhiyun  * OFF: The regulator is switched off and the output voltage is discharged.
136*4882a593Smuzhiyun  * PFM: In this mode, the regulator is always in PFM mode, which is useful
137*4882a593Smuzhiyun  *      at light loads for optimized efficiency.
138*4882a593Smuzhiyun  * PWM: In this mode, the regulator is always in PWM mode operation
139*4882a593Smuzhiyun  *	regardless of load conditions.
140*4882a593Smuzhiyun  * APS: In this mode, the regulator moves automatically between pulse
141*4882a593Smuzhiyun  *	skipping mode and PWM mode depending on load conditions.
142*4882a593Smuzhiyun  *
143*4882a593Smuzhiyun  * SWxMODE[3:0]
144*4882a593Smuzhiyun  * Normal Mode  |  Standby Mode	|      value
145*4882a593Smuzhiyun  *   OFF		OFF		0x0
146*4882a593Smuzhiyun  *   PWM		OFF		0x1
147*4882a593Smuzhiyun  *   PFM		OFF		0x3
148*4882a593Smuzhiyun  *   APS		OFF		0x4
149*4882a593Smuzhiyun  *   PWM		PWM		0x5
150*4882a593Smuzhiyun  *   PWM		APS		0x6
151*4882a593Smuzhiyun  *   APS		APS		0x8
152*4882a593Smuzhiyun  *   APS		PFM		0xc
153*4882a593Smuzhiyun  *   PWM		PFM		0xd
154*4882a593Smuzhiyun  */
155*4882a593Smuzhiyun #define OFF_OFF		0x0
156*4882a593Smuzhiyun #define PWM_OFF		0x1
157*4882a593Smuzhiyun #define PFM_OFF		0x3
158*4882a593Smuzhiyun #define APS_OFF		0x4
159*4882a593Smuzhiyun #define PWM_PWM		0x5
160*4882a593Smuzhiyun #define PWM_APS		0x6
161*4882a593Smuzhiyun #define APS_APS		0x8
162*4882a593Smuzhiyun #define APS_PFM		0xc
163*4882a593Smuzhiyun #define PWM_PFM		0xd
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun enum swx {
166*4882a593Smuzhiyun 	SW1 = 0,
167*4882a593Smuzhiyun 	SW2,
168*4882a593Smuzhiyun 	SW3,
169*4882a593Smuzhiyun 	SW4,
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun int mc34vr500_get_sw_volt(uint8_t sw);
173*4882a593Smuzhiyun int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt);
174*4882a593Smuzhiyun int power_mc34vr500_init(unsigned char bus);
175*4882a593Smuzhiyun #endif /* __MC34VR500_PMIC_H_ */
176