1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 Samsung Electronics 3*4882a593Smuzhiyun * Lukasz Majewski <l.majewski@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __MAX8998_PMIC_H_ 9*4882a593Smuzhiyun #define __MAX8998_PMIC_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* MAX 8998 registers */ 12*4882a593Smuzhiyun enum { 13*4882a593Smuzhiyun MAX8998_REG_IRQ1, 14*4882a593Smuzhiyun MAX8998_REG_IRQ2, 15*4882a593Smuzhiyun MAX8998_REG_IRQ3, 16*4882a593Smuzhiyun MAX8998_REG_IRQ4, 17*4882a593Smuzhiyun MAX8998_REG_IRQM1, 18*4882a593Smuzhiyun MAX8998_REG_IRQM2, 19*4882a593Smuzhiyun MAX8998_REG_IRQM3, 20*4882a593Smuzhiyun MAX8998_REG_IRQM4, 21*4882a593Smuzhiyun MAX8998_REG_STATUS1, 22*4882a593Smuzhiyun MAX8998_REG_STATUS2, 23*4882a593Smuzhiyun MAX8998_REG_STATUSM1, 24*4882a593Smuzhiyun MAX8998_REG_STATUSM2, 25*4882a593Smuzhiyun MAX8998_REG_CHGR1, 26*4882a593Smuzhiyun MAX8998_REG_CHGR2, 27*4882a593Smuzhiyun MAX8998_REG_LDO_ACTIVE_DISCHARGE1, 28*4882a593Smuzhiyun MAX8998_REG_LDO_ACTIVE_DISCHARGE2, 29*4882a593Smuzhiyun MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, 30*4882a593Smuzhiyun MAX8998_REG_ONOFF1, 31*4882a593Smuzhiyun MAX8998_REG_ONOFF2, 32*4882a593Smuzhiyun MAX8998_REG_ONOFF3, 33*4882a593Smuzhiyun MAX8998_REG_ONOFF4, 34*4882a593Smuzhiyun MAX8998_REG_BUCK1_VOLTAGE1, 35*4882a593Smuzhiyun MAX8998_REG_BUCK1_VOLTAGE2, 36*4882a593Smuzhiyun MAX8998_REG_BUCK1_VOLTAGE3, 37*4882a593Smuzhiyun MAX8998_REG_BUCK1_VOLTAGE4, 38*4882a593Smuzhiyun MAX8998_REG_BUCK2_VOLTAGE1, 39*4882a593Smuzhiyun MAX8998_REG_BUCK2_VOLTAGE2, 40*4882a593Smuzhiyun MAX8998_REG_BUCK3, 41*4882a593Smuzhiyun MAX8998_REG_BUCK4, 42*4882a593Smuzhiyun MAX8998_REG_LDO2_LDO3, 43*4882a593Smuzhiyun MAX8998_REG_LDO4, 44*4882a593Smuzhiyun MAX8998_REG_LDO5, 45*4882a593Smuzhiyun MAX8998_REG_LDO6, 46*4882a593Smuzhiyun MAX8998_REG_LDO7, 47*4882a593Smuzhiyun MAX8998_REG_LDO8_LDO9, 48*4882a593Smuzhiyun MAX8998_REG_LDO10_LDO11, 49*4882a593Smuzhiyun MAX8998_REG_LDO12, 50*4882a593Smuzhiyun MAX8998_REG_LDO13, 51*4882a593Smuzhiyun MAX8998_REG_LDO14, 52*4882a593Smuzhiyun MAX8998_REG_LDO15, 53*4882a593Smuzhiyun MAX8998_REG_LDO16, 54*4882a593Smuzhiyun MAX8998_REG_LDO17, 55*4882a593Smuzhiyun MAX8998_REG_BKCHR, 56*4882a593Smuzhiyun MAX8998_REG_LBCNFG1, 57*4882a593Smuzhiyun MAX8998_REG_LBCNFG2, 58*4882a593Smuzhiyun PMIC_NUM_OF_REGS, 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define MAX8998_LDO3 (1 << 2) 62*4882a593Smuzhiyun #define MAX8998_LDO4 (1 << 1) 63*4882a593Smuzhiyun #define MAX8998_LDO7 (1 << 6) 64*4882a593Smuzhiyun #define MAX8998_LDO8 (1 << 5) 65*4882a593Smuzhiyun #define MAX8998_LDO17 (1 << 4) 66*4882a593Smuzhiyun #define MAX8998_SAFEOUT1 (1 << 4) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define MAX8998_I2C_ADDR (0xCC >> 1) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun enum { LDO_OFF, LDO_ON }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* __MAX8998_PMIC_H_ */ 73